There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.