公开(公告)号：US20240318028A1

公开(公告)日：2024-09-26

申请号：US18436782

申请日：2024-02-08

申请人： SAMSUNG ELECTRONICS CO., LTD. ,  KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

发明人： Kihun JEONG ,  Youngdeog KOH ,  Yongchan KIM ,  Kookjeong SEO ,  Jihun SEO ,  Jungsoo LIM ,  Changho HAN ,  Daewon KIM ,  Jeongwoo ROH ,  Eunji LEE ,  Joonbum LEE

IPC分类号： C09D133/14 ,  C09D5/00 ,  C09D7/61 ,  C09D7/63 ,  C09D133/08 ,  C09D143/02

CPC分类号： C09D133/14 ,  C09D5/00 ,  C09D7/61 ,  C09D7/63 ,  C09D133/08 ,  C09D143/02

摘要： Disclosed are an anti-frost hydrogel coating composition including an ionic monomer, a method of forming an anti-frost hydrogel coating film on a substrate, and a heat exchanger including the anti-frost hydrogel coating film, the anti-frost hydrogel coating composition can include: an ionic monomer; a crosslinker including two or more acrylic groups; a polymerization initiator; and a solvent, and the ionic monomer can include at least one ionic monomer from among a zwitterionic monomer, a cationic monomer, and an anionic monomer.

公开(公告)号：US20160085903A1

公开(公告)日：2016-03-24

申请号：US14843491

申请日：2015-09-02

申请人： Samsung Electronics Co., Ltd.

发明人： Changho HAN

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/505

摘要： There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.

摘要翻译： 提供了一种在布局验证系统中验证基于Fin的集成电路布局的方法。 该方法包括接收与特定集成电路单元相对应的布局，从布局中提取一个或多个设备代码，以及根据门线序列使用一个或多个提取的设备代码合成码流。 每个设备代码基于布局中的相应的栅极线单元，其包括有源区域，栅极线以及与布局的硅散热片的多个相交点。

公开(公告)号：US20160085904A1

公开(公告)日：2016-03-24

申请号：US14844420

申请日：2015-09-03

申请人： Samsung Electronics Co., Ltd.

发明人： Taejoong SONG ,  Jung-Ho DO ,  Changho HAN

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G01R31/2882 ,  G06F2217/14

摘要： A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.

摘要翻译： 提供半导体器件的半导体器件和布局验证方法。 布局验证方法包括在半导体器件的衬底上形成多个标准单元，每个标准单元具有第一类型的交叉耦合结构（XC）和第二类型的XC，形成多个第一反相器，其中第一类型 在多个标准单元中激活XC的多个标准单元以及多个第二反相器，其中第二类型的XC在多个标准单元中被激活并且估计第一类型的XC的电特性或 通过测量多个第一反相器或多个第二反相器的信号延迟的大小来确定第二类型的XC。