Invention Application
- Patent Title: METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Application No.: US14962556Application Date: 2015-12-08
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Publication No.: US20160093555A1Publication Date: 2016-03-31
- Inventor: Yasuhiro TAKEDA , Takao KUMIHASHI , Hiroshi YANAGITA , Takashi TAKEUCHI , Yasushi MATSUDA
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2012-069669 20120326
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/532 ; H01L21/768

Abstract:
The TSV technology has been popular as one of stacking technologies of a plurality of semiconductor chips. It has however been revealed by the present inventors that when TSV is formed using a so-called first via process, via middle process, front-via via last process, or the like, there is a possibility of defects such as gate breakdown occurring due to electrostatic breakdown in the subsequent process. In order to overcome the above problem, the present invention provides a method of manufacturing a semiconductor integrated circuit device, in which a through via electrode is formed by forming a hole in a semiconductor substrate, forming an insulating member in the hole, and burying a conductive member in the resulting hole while covering a portion of the hole except for the bottom portion with the insulating member.
Information query
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