Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.