Invention Application
US20160126312A1 SEMICONDUCTOR STRUCTURE INCLUDING A DOPED BUFFER LAYER AND A CHANNEL LAYER AND A PROCESS OF FORMING THE SAME
审中-公开
包括DOPED缓冲层和通道层的半导体结构及其形成过程
- Patent Title: SEMICONDUCTOR STRUCTURE INCLUDING A DOPED BUFFER LAYER AND A CHANNEL LAYER AND A PROCESS OF FORMING THE SAME
- Patent Title (中): 包括DOPED缓冲层和通道层的半导体结构及其形成过程
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Application No.: US14867131Application Date: 2015-09-28
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Publication No.: US20160126312A1Publication Date: 2016-05-05
- Inventor: Peter MOENS
- Applicant: Semiconductor Components Industries, LLC
- Applicant Address: US AZ Phoenix
- Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
- Current Assignee Address: US AZ Phoenix
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/20 ; H01L29/66 ; H01L29/778

Abstract:
A semiconductor structure can include a substrate, a high-voltage blocking layer overlying the substrate, a doped buffer layer overlying the high-voltage layer, and a channel layer overlying the doped buffer layer, wherein the doped buffer layer and the channel layer include a same compound semiconductor material, and the doped buffer layer has a carrier impurity type at a first carrier impurity concentration, the channel buffer layer has the carrier impurity type at a second carrier impurity concentration that is less than the first carrier impurity concentration. In an embodiment, the channel layer has a thickness of at least 650 nm. In another embodiment, the high-voltage blocking includes a proximal region that is 1000 nm thick and adjacent to the doped buffer layer, and each of the proximal region, the doped buffer layer, and the channel layer has an Fe impurity concentration less than 5×1015 atoms/cm3.
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Information query
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