Invention Application
- Patent Title: SEMICONDUCTOR DEVICE
- Patent Title (中): 半导体器件
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Application No.: US14927056Application Date: 2015-10-29
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Publication No.: US20160126313A1Publication Date: 2016-05-05
- Inventor: Yoichi MIMURO
- Applicant: SEIKO INSTRUMENTS INC.
- Priority: JP2014-224330 20141104
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L29/423 ; H01L29/78

Abstract:
Provided is an integrated circuit having a LOCOS-drain type MOS transistor mounted thereon in which, even in the case of poor pattern formation, a withstand voltage is not lowered and a poor withstand voltage does not result. A drain oxide film thicker than a gate oxide film is formed on an active region on a drain side of the LOCOS-drain type MOS transistor, to thereby prevent the withstand voltage of the MOS transistor from being lowered even if the gate electrode reaches the active region on the drain side.
Public/Granted literature
- US09818832B2 Semiconductor device Public/Granted day:2017-11-14
Information query
IPC分类: