公开(公告)号：US20160126313A1

公开(公告)日：2016-05-05

申请号：US14927056

申请日：2015-10-29

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Yoichi MIMURO

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/42368 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

Abstract: Provided is an integrated circuit having a LOCOS-drain type MOS transistor mounted thereon in which, even in the case of poor pattern formation, a withstand voltage is not lowered and a poor withstand voltage does not result. A drain oxide film thicker than a gate oxide film is formed on an active region on a drain side of the LOCOS-drain type MOS transistor, to thereby prevent the withstand voltage of the MOS transistor from being lowered even if the gate electrode reaches the active region on the drain side.

Abstract translation: 提供了其上安装有LOCOS-漏极型MOS晶体管的集成电路，其中即使在图案形成差的情况下，耐压也不降低，并且不会导致差的耐受电压。 在LOCOS漏极型MOS晶体管的漏极侧的有源区域上形成比栅极氧化膜更厚的漏极氧化膜，从而即使栅电极达到活性，也可以防止MOS晶体管的耐电压降低 漏极侧的区域。

公开(公告)号：US20160126155A1

公开(公告)日：2016-05-05

申请号：US14927040

申请日：2015-10-29

Applicant: SEIKO INSTRUMENTS INC.

Inventor： Yoichi MIMURO ,  Kotaro WATANABE ,  Yukimasa MINAMI

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L21/563 ,  H01L23/562 ,  H01L29/0657 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2924/00

Abstract: Provided is a flip-chip mounted semiconductor device in which a crack is less likely to develop. Flip chip mounting is carried out under the condition that no oxide film exists on the scribe region so as to eliminate the interface between the oxide film that remains on the scribe region and the silicon substrate from which a crack may develop. As a result, the circuit board, the encapsulant, and the silicon substrate are stacked at an end portion of the semiconductor chip.

Abstract translation: 提供了一种倒装芯片安装的半导体器件，其中裂纹不太可能发展。 在划片区域上不存在氧化膜的情况下进行倒装芯片安装，以消除残留在划刻区域上的氧化膜与可能产生裂纹的硅衬底之间的界面。 结果，电路板，密封剂和硅衬底堆叠在半导体芯片的端部。