Invention Application
- Patent Title: HEADER PARITY ERROR HANDLING
- Patent Title (中): HEADER PARITY错误处理
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Application No.: US14553692Application Date: 2014-11-25
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Publication No.: US20160147592A1Publication Date: 2016-05-26
- Inventor: Jayakrishna Guddeti
- Applicant: Intel Corporation
- Main IPC: G06F11/10
- IPC: G06F11/10 ; H04L29/06 ; H04L1/00

Abstract:
A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.
Public/Granted literature
- US09749448B2 Header parity error handling Public/Granted day:2017-08-29
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