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    Apparatus, method, and system for early deep sleep state exit of a processing element
    1.
    发明授权
    Apparatus, method, and system for early deep sleep state exit of a processing element 有权
    处理元件早期深度睡眠状态退出的装置，方法和系统

    公开(公告)号：US09454218B2

    公开(公告)日：2016-09-27

    申请号：US14659253

    申请日：2015-03-16

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti ,  Binata Bhattacharyya

    IPC: G06F13/24 ,  G06F1/32 ,  G06F9/44

    CPC classification number: G06F1/3287 ,  G06F1/3228 ,  G06F1/329 ,  G06F9/4418 ,  G06F13/24 ,  Y02D10/24 ,  Y02D50/20

    Abstract: An apparatus and method is described herein for providing an early wake scheme before spawning a new thread. An early wake indication may be provided an amount of time, which may include an amount of time to perform a demotion from a current power state to a lower power state that is closer to an active power state, before a new thread is to be spawned and executed on a processing element (e.g., core or thread). Upon encountering the spawn of the new thread, such as a helper thread, the processing element may further transition from the lower power state to an active power state. The new thread may be executed on the processing element without incurring the latency associated with execution of the new thread waiting for the demotion from the current power state to an active power state after the spawn of the new thread.

    Abstract translation: 本文描述了一种在产生新线程之前提供早期唤醒方案的装置和方法。 早期的唤醒指示可以在新线程被产生之前提供一定的时间量，其可以包括执行从当前功率状态降级到更靠近有功功率状态的较低功率状态的时间量 并在处理元件（例如，核心或线程）上执行。 在遇到诸如辅助线程的新线程的产生时，处理元件可以进一步从较低功率状态转换到有功功率状态。 可以在处理元件上执行新线程，而不会在新线程的产生之后产生等待从当前功率状态到有功功率状态的新线程的执行相关联的延迟。

    HEADER PARITY ERROR HANDLING
    3.
    发明申请
    HEADER PARITY ERROR HANDLING 有权
    HEADER PARITY错误处理

    公开(公告)号：US20160147592A1

    公开(公告)日：2016-05-26

    申请号：US14553692

    申请日：2014-11-25

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti

    IPC: G06F11/10 ,  H04L29/06 ,  H04L1/00

    CPC classification number: H04L69/22 ,  H04L1/0056 ,  H04L1/0061 ,  H04L1/0082

    Abstract: A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

    Abstract translation: 在标题中检测到奇偶校验错误，其中报头在多个队列中的特定一个中，报头将包括多个字段，并且每个队列都对应于相应的事务类型。 为多个字段中的一个或多个字段生成编制标题数据以指示奇偶校验错误并替换多个字段中的一个或多个字段的数据。 基于奇偶校验错误输入错误容纳模式。

    Increasing turbo mode residency of a processor
    4.
    发明授权
    Increasing turbo mode residency of a processor 有权
    增加处理器的turbo模式驻留

    公开(公告)号：US09032125B2

    公开(公告)日：2015-05-12

    申请号：US13780075

    申请日：2013-02-28

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti ,  Binata Bhattacharyya

    IPC: G06F9/50 ,  G06F13/24 ,  G06F1/32 ,  G06F1/20

    CPC classification number: G06F13/24 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/5038 ,  G06F9/5094 ,  Y02D10/22

    Abstract: In one embodiment, the present invention includes a method for accessing a task stored in an entry of a task queue that identifies the task and a first core of a processor on which the task has been scheduled, reassigning the task to a coldest idle core of the processor, and sending the task to the coldest idle core and maintaining the processor in a turbo mode. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括一种用于访问存储在任务队列的条目中的任务的方法，所述任务识别任务，并且处理器的第一核心已经被安排在其上，将任务重新分配到最冷空闲核心 处理器，并将任务发送到最冷的空闲核心并将处理器维持在turbo模式。 描述和要求保护其他实施例。

    Header parity error handling
    5.
    发明授权
    Header parity error handling 有权

    公开(公告)号：US09749448B2

    公开(公告)日：2017-08-29

    申请号：US14553692

    申请日：2014-11-25

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti

    IPC: H04L1/18 ,  H04L29/06 ,  H04L1/00

    CPC classification number: H04L69/22 ,  H04L1/0056 ,  H04L1/0061 ,  H04L1/0082

    Abstract: A parity error is detected in a header, where the header is in a particular one of a plurality of queues, the header is to include a plurality of fields, and each of the queues is to correspond to a respective transaction type. Fabricated header data is generated for one or more of the plurality of fields to indicate the parity error and replace data of one or more of the plurality of fields. An error containment mode is entered based on the parity error.

    POSTED INTERRUPT ARCHITECTURE
    6.
    发明申请
    POSTED INTERRUPT ARCHITECTURE 有权
    中断中断架构

    公开(公告)号：US20160147679A1

    公开(公告)日：2016-05-26

    申请号：US14553430

    申请日：2014-11-25

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti ,  Luke Chang ,  Rajesh M. Sankaran ,  Junaid F. Thaliyil

    IPC: G06F13/24 ,  G06F12/08

    CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F9/4812 ,  G06F12/0871 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2212/1032 ,  G06F2212/657

    Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

    Abstract translation: 从输入/输出（I / O）设备识别中断，特定高速缓存行的地址与中断相关联。 高速缓存行对应于中断的目的地，并表示中断的一个或多个属性。 一个请求被发送到一个并发代理以获取特定高速缓存行的所有权，并且发送一个请求，以便基于该中断在高速缓存行上执行读 - 修改 - 写（RMW）操作。

    Dual casting PCIE inbound writes to memory and peer devices
    7.
    发明授权
    Dual casting PCIE inbound writes to memory and peer devices 有权
    双向PCIE入卡写入内存和对等设备

    公开(公告)号：US09189441B2

    公开(公告)日：2015-11-17

    申请号：US13656134

    申请日：2012-10-19

    Applicant: INTEL CORPORATION

    Inventor： Jayakrishna Guddeti ,  Luke Chang

    IPC: G06F13/14 ,  G06F13/40

    CPC classification number: G06F13/404 ,  G06F13/14 ,  G06F2213/0026

    Abstract: Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory write request from a first PCIe device is received at a PCIe root complex and the memory address is inspected to determine whether it falls within an address window defined for dual casting operations. If it does, an IO write request is generated from the inbound system memory write request and sent to a second PCIe device associated with the address window. During a parallel operation, the original inbound system memory write request is forwarded to a system agent configured to receive such write requests.

    Abstract translation: 用于支持从PCIe设备到存储器和对等PCIe设备的入站系统存储器双向注入的方法和设备。 在PCIe根组合处接收来自第一PCIe设备的入站系统存储器写入请求，并检查存储器地址以确定其是否落入为双重铸造操作定义的地址窗口内。 如果是这样，则从入站系统存储器写请求产生IO写请求，并将其发送到与地址窗口相关联的第二PCIe设备。 在并行操作期间，将原始入站系统内存写请求转发给配置为接收此类写请求的系统代理。

    Method, apparatus and system to implement secondary bus functionality via a reconfigurable virtual switch
    9.
    发明授权
    Method, apparatus and system to implement secondary bus functionality via a reconfigurable virtual switch 有权

    公开(公告)号：US10210120B2

    公开(公告)日：2019-02-19

    申请号：US14669256

    申请日：2015-03-26

    Applicant: Intel Corporation

    Inventor： Jayakrishna Guddeti

    IPC: H05K7/10 ,  G06F13/40

    Abstract: In an embodiment, an apparatus includes: a fabric of a first communication protocol to communicate with an upstream agent in an upstream direction and to communicate with a plurality of downstream agents in a downstream direction; a switch coupled between the fabric and at least some of the plurality of downstream agents, the switch to couple to a primary interface of the fabric via a primary interface of the switch and to communicate with the fabric via the first communication protocol, the switch further including a sideband interface to interface with a sideband fabric of the first communication protocol; and the at least some downstream agents coupled to the switch via the sideband fabric, wherein the at least some downstream agents are to be enumerated with a secondary bus of a second communication protocol, and the switch device is to provide a transaction received from the upstream agent to a first downstream agent based on a bus identifier of the secondary bus with which the first downstream agent is enumerated. Other embodiments are described and claimed.

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