Invention Application
- Patent Title: METHODS AND APPARATUSES WITH VERTICAL STRINGS OF MEMORY CELLS AND SUPPORT CIRCUITRY
-
Application No.: US15011819Application Date: 2016-02-01
-
Publication No.: US20160148943A1Publication Date: 2016-05-26
- Inventor: Takehiro Hasegawa , Koji Sakui
- Applicant: Micron Technology, Inc.
- Main IPC: H01L27/115
- IPC: H01L27/115 ; H01L21/28

Abstract:
Apparatuses and methods have been disclosed. One such apparatus includes strings of memory cells formed on a topside of a substrate. Support circuitry is formed on the backside of the substrate and coupled to the strings of memory cells through vertical interconnects in the substrate. The vertical interconnects can be transistors, such as surround substrate transistors and/or surround gate transistors.
Public/Granted literature
- US10319729B2 Methods and apparatuses with vertical strings of memory cells and support circuitry Public/Granted day:2019-06-11
Information query
IPC分类: