Invention Application
US20160149729A1 MULTI-WIRE SYMBOL TRANSITION CLOCKING SYMBOL ERROR CORRECTION 有权
多线符号转换时钟符号错误校正

  • Patent Title: MULTI-WIRE SYMBOL TRANSITION CLOCKING SYMBOL ERROR CORRECTION
  • Patent Title (中): 多线符号转换时钟符号错误校正
  • Application No.: US14949290
    Application Date: 2015-11-23
  • Publication No.: US20160149729A1
    Publication Date: 2016-05-26
  • Inventor: Shoichiro Sengoku
  • Applicant: QUALCOMM Incorporated
  • Main IPC: H04L25/03
  • IPC: H04L25/03 H04L27/38
MULTI-WIRE SYMBOL TRANSITION CLOCKING SYMBOL ERROR CORRECTION
Abstract:
Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.
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