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公开(公告)号：US10089173B2
公开(公告)日：2018-10-02
申请号：US14949435
申请日：2015-11-23
发明人： Shoichiro Sengoku
IPC分类号： G06F11/10 , H03M13/00 , H03M13/03 , H03M5/00 , H04L1/00 , H04L25/02 , H04L25/03 , H04L25/14 , H04L25/493 , H04L27/38 , H04L1/24 , H04L7/033
摘要： Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for transmitting data on the multi-wire interface includes transmitting data on a multi-wire interface includes obtaining a plurality of bits to be transmitted over a plurality of connectors, converting the plurality of bits into a sequence of symbols, and transmitting the sequence of symbols on the plurality of connectors. A predetermined number of least significant bits in the plurality of bits may be used for error detection. The predetermined number of least significant bits may have a constant value that is different from each of a plurality of error values. A symbol error affecting one or two symbols in the sequence of symbols may cause a decoded version of the predetermined number of least significant bits to have value that is one of a plurality of error values.
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公开(公告)号：US10031547B2
公开(公告)日：2018-07-24
申请号：US14572680
申请日：2014-12-16
发明人： Shoichiro Sengoku
摘要： Methods, apparatus, and computer program products are described, which provide a mechanism that enables data to be written into registers of a slave device without a free-running clock, while facilitating an efficient sleep and wakeup mechanism for slave devices. A receiver device may receive a plurality of symbols over a shared bus, extract a receive clock signal embedded in symbol-to-symbol transitions of the plurality of symbols, convert the plurality of symbols into a transition number, convert the transition number into data bits, and store at least a portion of the data bits into one or more registers using only the receive clock signal. The receiver device may start a down counter upon detection of a first cycle of the clock signal, trigger a marker when the down counter reaches a pre-defined value, and use the marker to store at least a portion of the data bits into registers.
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公开(公告)号：US20170220518A1
公开(公告)日：2017-08-03
申请号：US15486217
申请日：2017-04-12
IPC分类号： G06F13/42 , G06F13/364
CPC分类号： G06F13/4291 , G06F13/364 , G06F13/4282 , G06F13/4295 , H04L7/0331
摘要： System, methods and apparatus are described that offer improved performance of a serial bus used for Inter-Integrated Circuit (I2C) and/or camera control interface (CCI) operations. Other described devices may be configured as a bus master or as a slave. In one method, a transmitter may generate a transition number from a set of bits, convert the transition number into a sequence of symbols, and transmit the sequence of symbols in the signaling state of a two-wire serial bus. Timing information may be encoded in the transitions between symbols of consecutive pairs of symbols in the sequence of symbols. For example, each transition may cause a change in the signaling state of at least one wire of the two-wire serial bus. A receiver may derive a receive clock from the transitions in order to receive and decode the sequence of symbols.
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公开(公告)号：US20170201370A1
公开(公告)日：2017-07-13
申请号：US15470479
申请日：2017-03-27
发明人： Shoichiro Sengoku
CPC分类号： H04L7/0045 , G06F1/12 , H03K5/13 , H03K5/133 , H03K5/1534 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L25/49
摘要： A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.
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公开(公告)号：US20170104607A1
公开(公告)日：2017-04-13
申请号：US14882011
申请日：2015-10-13
发明人： Shoichiro Sengoku
IPC分类号： H04L12/40 , H04L29/06 , H04L12/403
CPC分类号： H04L12/40019 , G06F13/4291 , H04L12/403 , H04L69/18
摘要： System, methods and apparatus offer improved coexistence of devices on a serial bus. A bus master coupled to a serial bus transmits a start condition on the serial bus, and a first series of pulses on a clock line of the serial bus, the pulses having a duration that is less than a maximum duration for spikes to be filtered in accordance with the I2C protocol. The bus master transmits a second series of pulses on the clock line, the pulses having a duration that is greater than or equal to a minimum duration for clock pulses defined by the I2C protocol, and uses the second series of pulses to transmit a data frame on the serial bus in accordance with a different protocol. A stop condition is transmitted on the serial bus in accordance with the I2C protocol after transmission of the data frame is completed.
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公开(公告)号：US20160301519A1
公开(公告)日：2016-10-13
申请号：US15084171
申请日：2016-03-29
发明人： Shoichiro Sengoku
IPC分类号： H04L7/00
CPC分类号： H04L7/0045 , G06F1/12 , H03K5/13 , H03K5/133 , H03K5/1534 , H04L7/0037 , H04L7/0087 , H04L7/033 , H04L25/49
摘要： A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a plurality of input latches configured to assume a first state when a first pulse is received in one or more of a plurality of input signals, combinational logic configured to provide a second pulse response to the first pulse, a delay circuit configured to produce a third pulse on a receive clock that is delayed with respect to the second pulse, a plurality of output flip-flops configured to capture the first state when triggered by the third pulse. The first state may identify which of the plurality of input signals received input pulses.
摘要翻译： 提供了一种方法和装置。 该装置可以包括具有多个输入锁存器的时钟恢复电路，所述多个输入锁存器被配置为当在多个输入信号中的一个或多个中接收到第一脉冲时呈现第一状态，组合逻辑被配置为向第一脉冲提供第二脉冲响应 延迟电路，被配置为在相对于所述第二脉冲延迟的接收时钟上产生第三脉冲;多个输出触发器，被配置为当由所述第三脉冲触发时捕获所述第一状态。 第一状态可以识别接收的多个输入信号中的哪一个输入脉冲。
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7.发明申请FAREWELL RESET AND RESTART METHOD FOR COEXISTENCE OF LEGACY AND NEXT GENERATION DEVICES OVER A SHARED MULTI-MODE BUS 审中-公开FAREWELL复位和重新启动方法，用于共享和下一个生成设备在共享的多模式总线公开(公告)号：US20160195910A1
公开(公告)日：2016-07-07
申请号：US15067111
申请日：2016-03-10
发明人： Shoichiro Sengoku
CPC分类号： G06F1/24 , G06F13/4022 , G06F13/4027 , G06F13/4282 , G06F13/4291 , G06F13/4295
摘要： A first set of devices is coupled to a first bus, a second bus, and configured to communicate over the first bus according to a first communication protocol. A second set of devices is also coupled to the first bus and configured to communicate over the first bus according to both the first communication protocol and a second communication protocol. In a first mode, the first set of devices and second set of devices may concurrently communicate over the first bus using the first communication protocol. In a second mode, the second set of devices communicate using the second communication protocol over the bus, and the first set of devices to stop operating on the first bus. An enable command is sent by at least one of the second set of devices over a second bus to cause the first set of devices to resume activity over the first bus.
摘要翻译： 第一组设备耦合到第一总线，第二总线，并且被配置为根据第一通信协议通过第一总线进行通信。 第二组设备还耦合到第一总线并且被配置为根据第一通信协议和第二通信协议通过第一总线进行通信。 在第一模式中，第一组设备和第二组设备可以使用第一通信协议通过第一总线同时进行通信。 在第二模式中，第二组设备使用总线上的第二通信协议进行通信，并且第一组设备在第一总线上停止操作。 通过第二总线由第二组设备中的至少一个发送使能命令，以使得第一组设备在第一总线上恢复活动。
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8.发明申请SYMBOL TRANSITION CLOCKING CLOCK AND DATA RECOVERY TO SUPPRESS EXCESS CLOCK CAUSED BY SYMBOL GLITCH DURING STABLE SYMBOL PERIOD 有权符号转换时钟和数据恢复在符号符号周期内超过符号时间引起的超时时钟公开(公告)号：US20160149693A1
公开(公告)日：2016-05-26
申请号：US14555097
申请日：2014-11-26
发明人： Shoichiro Sengoku
CPC分类号： H04L7/0087 , G06F13/4072 , G11C8/06 , H04L7/0037 , H04L7/0083 , H04L7/033 , H04L7/042 , H04L7/08 , H04L25/14 , H04L25/49
摘要： A method and an apparatus are provided. The apparatus may includes a clock recovery circuit having a comparator that provides a comparison signal indicating whether an input signal matches a level-latched instance of the input signal, a first set-reset latch that provides a filtered version of the comparison signal, where the first set-reset latch is set by a first-occurring active transition of the comparison signal and is unaffected by further transitions of the comparison signal that occur during a predefined period of time, delay circuitry that receives the filtered version of the comparison signal and outputs a first pulse on a first clock signal, and a second set-reset latch configured to provide a second pulse on an output clock signal when the first pulse is present on the first clock signal and the comparison signal indicates that the level-latched instance of the input signal does not match the input signal.
摘要翻译： 提供了一种方法和装置。 该装置可以包括具有比较器的时钟恢复电路，该比较器提供指示输入信号是否匹配输入信号的电平锁存实例的比较信号，提供比较信号的滤波版本的第一设置复位锁存器，其中 第一设置复位锁存器由比较信号的第一次有效转换设置，并且不受在预定时间段期间发生的比较信号的进一步转换的影响，接收比较信号的滤波版本的延迟电路和输出 第一时钟信号上的第一脉冲和第二设置复位锁存器，其被配置为当第一时钟信号上存在第一脉冲时，在输出时钟信号上提供第二脉冲，并且比较信号指示电平锁存的实例 输入信号与输入信号不匹配。
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9.发明授权公开(公告)号：US09319178B2
公开(公告)日：2016-04-19
申请号：US14214285
申请日：2014-03-14
发明人： Shoichiro Sengoku
CPC分类号： H04L1/0041 , G06F13/40 , H03M5/14 , H03M13/05 , H03M13/31 , H04L1/0042 , H04L1/0057 , H04L25/0272 , H04L25/14 , H04L2001/0094
摘要： System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A data payload may be converted to a set of transition numbers, the transition numbers may be converted to a sequence of symbols and an error correction code (ECC) may be calculated from symbols in the sequence of symbols. The ECC corresponds to the data payload and the ECC may be appended to the data payload such that the set of transition numbers includes transition numbers corresponding to the ECC. The sequence of symbols is then transmitted on a plurality of signal wires. Clock information is encoded in the sequence of symbols. The clock information may be encoded by ensuring that each pair of consecutive symbols in the sequence of symbols includes two symbols that produce different signaling states on the plurality of signal wires.
摘要翻译： 描述了便于通过多线数据通信链路，特别是在电子设备内的两个设备之间传输数据的系统，方法和装置。 可以将数据有效载荷转换成一组转换号码，转换号码可以被转换成符号序列，并且可以从符号序列中的符号计算纠错码（ECC）。 ECC对应于数据有效载荷，并且ECC可以附加到数据有效载荷，使得该组转换号包括对应于ECC的转移号。 然后，在多条信号线上发送符号序列。 时钟信息以符号序列编码。 可以通过确保符号序列中的每对连续符号包括在多条信号线上产生不同信令状态的两个符号来编码时钟信息。
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10.发明授权Compact and fast N-factorial single data rate clock and data recovery circuits 有权紧凑，快速的N因子单数据速率时钟和数据恢复电路公开(公告)号：US09313058B2
公开(公告)日：2016-04-12
申请号：US14459132
申请日：2014-08-13
CPC分类号： H04L25/40 , H03L7/00 , H04L7/0276 , H04L7/033 , H04L7/04 , H04L25/14 , H04L25/493
摘要： A plurality of line interfaces is configured to receive a spread signal over the plurality of line interface. The spread signal carrying symbols with guaranteed symbol-to-symbol state transitions between consecutive symbols. The spread signal is defined by a plurality of transition signals including a first signal over a first line interface. A clock signal is extracted based on a comparison between a first instance of the first signal and a delayed second instance of the first signal. The delayed second instance of the first signal is sampled based on the clock signal to provide a symbol output. The clock extraction circuit is further adapted to generate the clock signal based on additional comparisons between a first instance of a second signal, within the plurality of transition signals, and a delayed second instance of the second signal, where the first and second signals are concurrent signals received over different line interfaces.
摘要翻译： 多个线路接口被配置为在多个线路接口上接收扩展信号。 扩展信号携带符号，其中连续符号之间保证符号到符号状态转换。 扩展信号由包括第一线路接口上的第一信号的多个转换信号定义。 基于第一信号的第一实例和第一信号的延迟的第二实例之间的比较来提取时钟信号。 基于时钟信号对第一信号的延迟第二实例进行采样以提供符号输出。 时钟提取电路还适于基于多个转换信号之间的第二信号的第一实例与第二信号的延迟的第二实例之间的附加比较来生成时钟信号，其中第一和第二信号是并发的 通过不同线路接口接收的信号。
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