Invention Application
- Patent Title: INTEGRATED CIRCUIT ASSEMBLIES WITH RIGID LAYERS USED FOR PROTECTION AGAINST MECHANICAL THINNING AND FOR OTHER PURPOSES, AND METHODS OF FABRICATING SUCH ASSEMBLIES
- Patent Title (中): 用于防止机械损伤和其他目的的刚性层的集成电路组件以及制造这种组件的方法
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Application No.: US14704714Application Date: 2015-05-05
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Publication No.: US20160163650A1Publication Date: 2016-06-09
- Inventor: Guilian GAO , Cyprian Emeka UZOH , Charles G. WOYCHIK , Hong SHEN , Arkalgud R. SITARAM , Liang WANG , Akash AGRAWAL , Rajesh KATKAR
- Applicant: Invensas Corporation
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/00 ; H01L23/00 ; H01L25/065

Abstract:
Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.
Public/Granted literature
Information query
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