公开(公告)号：US20180130717A1

公开(公告)日：2018-05-10

申请号：US15865842

申请日：2018-01-09

Applicant: INVENSAS CORPORATION

Inventor： Hong SHEN ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM

IPC: H01L23/055 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/04 ,  H01L23/14 ,  H01L23/31 ,  H01L23/367 ,  H01L23/48 ,  H01L21/288 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L23/10

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

公开(公告)号：US20170040237A1

公开(公告)日：2017-02-09

申请号：US15265148

申请日：2016-09-14

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L23/055 ,  H01L25/00 ,  H01L25/065 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Abstract translation: 具有集成电路的模具（110）附接到布线基板（120），可能是插入件，并且被附接到布线基板的保护基板（410）保护。 模具位于保护衬底中的空腔中（模具可能突出出腔体）。 在一些实施例中，每个空腔表面在模具上施加压力以加强模具与布线基板的机械连接，以在模具和环境（或散热器）之间提供良好的导热性以抵抗模具翘曲，并且可能 减小垂直尺寸。 保护衬底可以具有或不具有连接到管芯或布线衬底的其自身的电路。 还提供其他功能。

公开(公告)号：US20160163650A1

公开(公告)日：2016-06-09

申请号：US14704714

申请日：2015-05-05

Applicant: Invensas Corporation

Inventor： Guilian GAO ,  Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Hong SHEN ,  Arkalgud R. SITARAM ,  Liang WANG ,  Akash AGRAWAL ,  Rajesh KATKAR

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract translation: 模具（110）和/或未开封的晶片和/或多芯片模块（MCM）被附接在插入器（120）或一些其它结构（例如另一集成电路）的顶部上并被密封剂（160）覆盖。 然后插入器从下面变薄。 在封装之前，在封装周围的插入件周围形成比密封剂更刚性的层（410），以通过机械工艺（例如CMP）来减小或消除插入件在裸片间的凹陷。 还提供其他功能。

公开(公告)号：US20160013151A1

公开(公告)日：2016-01-14

申请号：US14328380

申请日：2014-07-10

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM

IPC: H01L25/065 ,  H01L21/52 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/5384 ,  H01L24/09 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/08165 ,  H01L2224/08235 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/8182 ,  H01L2224/85205 ,  H01L2224/9202 ,  H01L2224/92125 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.

Abstract translation: 半导体集成电路（110）或组件至少部分地设置在两个插入件（120）之间的空腔中。 导电通孔（204M）通过至少一个插入件或至少穿过插入器的衬底，并到达半导体集成电路或组件。 其他导电通孔（204M.1）至少部分地通过多个插入件并且连接到到达或者电容耦合到半导体IC或组件的导电通孔。 还提供其他功能。

公开(公告)号：US20150364538A1

公开(公告)日：2015-12-17

申请号：US14304535

申请日：2014-06-13

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/65 ,  H01L28/90 ,  H01L28/92 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Abstract translation: 在一个实施例中，制造3D金属 - 绝缘体 - 金属（MIM）电容器的方法包括提供具有表面的基板，在表面上形成直立杆或脊的阵列，在表面上沉积第一层电导体， 所述棒或脊的阵列，用电介质层涂覆所述第一导电层，以及在所述电介质层上沉积第二层电导体。 在一些实施例中，杆或脊的阵列可以由光致抗蚀剂材料制成，并且在另一些实施例中，可以包括接合线。

公开(公告)号：US20170018517A1

公开(公告)日：2017-01-19

申请号：US15203013

申请日：2016-07-06

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Liang WANG ,  Arkalgud R. SITARAM

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/09 ,  H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/53209 ,  H01L24/89 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/08168 ,  H01L2224/08501 ,  H01L2224/73204 ,  H01L2224/80487 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/05442 ,  H01L2924/1304 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.

Abstract translation: 两个微电子部件（110,120），例如 模具和插入件彼此结合。 部件的接触焊盘（110C）中的一个包括金属，另一部件具有与金属反应形成金属硅化物（504）的硅（410）。 然后通过其中一个部件制成一个孔（510），以到达金属硅化物，甚至可能连接另一部件的未反应的金属（110C）。 该孔填充有可能是金属的导体（130），以提供可电耦合到可附接到其它电路元件或微电子部件的接触焊盘（120C.B）的导电通孔，例如。 到印刷电路板。

公开(公告)号：US20160071818A1

公开(公告)日：2016-03-10

申请号：US14809036

申请日：2015-07-24

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  B81B7/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  B81C1/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/09 ,  B81B7/008 ,  B81B2207/07 ,  B81C1/0023 ,  H01L21/565 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/34 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/33517 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92133 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Abstract translation: 在多芯片模块（MCM）中，“超级”芯片（110N）被连接到多个“普通”芯片（110F“超”和“平原”芯片可以是任何芯片）。 超级芯片位于布线板（WB）上方，但位于平面芯片（110F）的至少一些之上。 普通芯片与超级芯片重叠。 此外，普通芯片的低速IO可以通过诸如接合线（例如BVA）或焊料堆的长直接连接连接到WB; 这种连接可以与超级芯片并排放置。 这种连接可能很长，所以超级芯片不需要很薄。 此外，如果省略通孔基板通孔（TSV），则制造成品率高，制造成本低。 提供了组合短和长直接连接以获得所需物理和电性能的其它结构。

公开(公告)号：US20170084539A1

公开(公告)日：2017-03-23

申请号：US15364534

申请日：2016-11-30

Applicant: Invensas Corporation

Inventor： Guilian GAO ,  Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Hong SHEN ,  Arkalgud R. SITARAM ,  Liang WANG ,  Akash AGRAWAL ,  Rajesh KATKAR

IPC: H01L23/538 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

公开(公告)号：US20170018510A1

公开(公告)日：2017-01-19

申请号：US15280175

申请日：2016-09-29

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Liang WANG ,  Rajesh KATKAR ,  Charles G. WOYCHIK ,  Guilian GAO

IPC: H01L23/00 ,  H01L23/053 ,  H01L23/498 ,  H01L23/31 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/481 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L23/053 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13111 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/16153 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/16315 ,  H01L2924/1632 ,  H01L2924/167 ,  H01L2924/16787 ,  H01L2924/16788 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/01029 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) are attached to an interposer (420), and the interposer/die assembly is placed into a lid cavity (510). The lid (210) is attached to the top of the assembly, possibly to the encapsulant (474) at the top. The lid's legs (520) surround the cavity and extend down below the top surface of the interposer's substrate (420S), possibly to the level of the bottom surface of the substrate or lower. The legs (520) may or may not be attached to the interposer/die assembly. In fabrication, the interposer wafer (420SW) has trenches (478) which receive the lid's legs during the lid placement. The interposer wafer is later thinned to remove the interposer wafer portion below the legs and to dice the interposer wafer. The thinning process also exposes, on the bottom, conductive vias (450) passing through the interposer substrate. Other features are also provided.

Abstract translation: 模具（110）附接到插入件（420），并且插入器/模具组件被放置在盖腔（510）中。 盖（210）附接到组件的顶部，可能附接到顶部的密封剂（474）。 盖的腿（520）围绕空腔并且向下延伸到插入器的衬底（420S）的顶表面下方，可能地到衬底的底表面的高度或更低。 腿（520）可以或可以不附接到插入件/模具组件。 在制造中，插入器晶片（420SW）具有在盖放置期间接收盖的腿的沟槽（478）。 中间层晶片稍后变薄以去除腿下方的插入片晶片部分并且切割插入片晶片。 薄化工艺还在底部暴露穿过内插衬底的导电通孔（450）。 还提供其他功能。

公开(公告)号：US20150327367A1

公开(公告)日：2015-11-12

申请号：US14275741

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Zhuowen Sun ,  Charles G. Woychik ,  Arkalgud Sitaram

IPC: H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1615 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

Abstract translation: 组合插入器（120）包括多个成分插入件（120.i），每个具有其自己的衬底（120.iS）并且在衬底的顶部和/或底部上具有电路层（例如再分配层）。 顶层电路层可以是可以互连不同插入件的公共电路层（120R.T）的一部分。 类似地，底部电路层可​​以是公共电路层（120R.B）的一部分。 成分插入器基板（120.iS）最初是公共晶片的一部分，并且在将成分插入器基板与晶片分离之前制造公共顶层电路层。 与使用单个大型基材相比，分离的基材的使用降低了应力。 还提供其他功能。