A gate driver IC (i.e., gate driver circuit), when set to a first mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with one clock cycle of a clock inputted to the terminal CLK** (clock input terminal), and outputs a selection voltage or a non-selection voltage based on a data position in the gate driver IC; and when set to a second mode by a logic signal of the tenninal FNC*, shifts data in the gate driver IC in synchronization with n clock cycles (n is an integer of at least 2) of a clock inputted to the terminal CLK**, and outputs the selection voltage or the non-selection voltage based on the data position in the gate driver IC.