公开(公告)号：US20170076664A1

公开(公告)日：2017-03-16

申请号：US15126082

申请日：2014-12-24

Applicant: JOLED INC.

Inventor： Hirofumi NAKAGAWA

IPC: G09G3/3225 ,  G09G3/36

CPC classification number: G09G3/3225 ,  G09G3/3266 ,  G09G3/3648 ,  G09G2300/0408 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2330/028

Abstract: A gate driver IC includes: N shift registers which generate a gate signal to be supplied to a display panel substrate, N being a natural number; (N+k) power supply terminals (PA1 to PD1, Pa1, and Pc1) for power supply from outside, k being a natural number; and (N+k) internal lines connected to the (N+k) power supply terminals, wherein N internal lines among the (N+k) internal lines connect, one-to-one, N power supply terminals among the (N+k) power supply terminals and the N shift registers, and k internal lines other than the N internal lines among the (N+k) internal lines connect, one-to-one, k power supply terminals other than the N power supply terminals among the (N+k) power supply terminals and k internal lines selected from among the N internal lines.

Abstract translation: 栅极驱动器IC包括：产生要提供给显示面板基板的栅极信号的N个移位寄存器，N是自然数; （N + k）个电源端子（PA1〜PD1，Pa1，Pc1），k为自然数; 和连接到所述（N + k）个电源端子的（N + k）个内部线路，其中，所述（N + k）个内部线路中的N条内部线路连接所述（N + k）个电源端子中的一对一N个电源端子， k个电源端子和N个移位寄存器，（N + k）个内部线路中的N个内部线路以外的k个内部线路与N个电源端子之间的1对1个k个电源端子连接， （N + k）个电源端子和从N条内部线路中选出的k条内部线路。

公开(公告)号：US20170263185A1

公开(公告)日：2017-09-14

申请号：US15509674

申请日：2015-09-02

Applicant: JOLED INC.

Inventor： Hirofumi NAKAGAWA

IPC: G09G3/3258

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3275 ,  G09G2310/0289 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/028 ,  H01L51/50

Abstract: A source driver circuit which supplies, to each of pixels arranged in a matrix, an electrical signal corresponding to a pixel signal, the source driver circuit including: a reference voltage generating unit including a plurality of resistors connected in series; a resistor for gradation voltage generation which divides an input voltage into voltages of magnitudes; and a gradation voltage generating circuit which is connected between the plurality of resistors and between the plurality of resistors and the resistor for gradation voltage generation, and includes an offset-canceling amplifier, wherein the offset-canceling amplifier alternates between an offset extraction state in which an offset voltage of the offset-canceling amplifier is extracted and a buffer output state in which the offset voltage is added to the pixel signal and outputted.

公开(公告)号：US20160307513A1

公开(公告)日：2016-10-20

申请号：US15101962

申请日：2014-04-10

Applicant: JOLED INC.

Inventor： Hirofumi NAKAGAWA ,  Hiroshi TAKAHARA

IPC: G09G3/3258

CPC classification number: G09G3/3258 ,  G09G3/3266 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28 ,  H01L27/3244

Abstract: A gate drive integrated circuit includes: clock terminals; a bidirectional buffer that is located between the clock terminals and controls the input-output direction of a clock signal; a connection mode control terminal that receives a connection mode control signal; and a pair of signal direction control terminals that receive a signal direction control signal, wherein the bidirectional buffer fixes the input-output direction of the clock signal to one direction in the case where the logic state of the connection mode control signal is a first logic state, and switches the input-output direction of the clock signal depending on the logic state of the signal direction control signal in the case where the logic state of the connection mode control signal is a second logic state different from the first logic state.

Abstract translation: 门驱动集成电路包括：时钟端子; 位于时钟端子之间的双向缓冲器，控制时钟信号的输入输出方向; 连接模式控制终端，其接收连接模式控制信号; 以及接收信号方向控制信号的一对信号方向控制端子，其中在连接模式控制信号的逻辑状态是第一逻辑的情况下，双向缓冲器将时钟信号的输入输出方向固定为一个方向 状态，并且在连接模式控制信号的逻辑状态是与第一逻辑状态不同的第二逻辑状态的情况下，根据信号方向控制信号的逻辑状态切换时钟信号的输入输出方向。

公开(公告)号：US20160171933A1

公开(公告)日：2016-06-16

申请号：US14904790

申请日：2014-07-03

Applicant: JOLED INC.

Inventor： Hiroshi TAKAHARA ,  Hirofumi NAKAGAWA

IPC: G09G3/32

CPC classification number: G09G3/3258 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G2300/0452 ,  G09G2300/0842 ,  G09G2300/0852 ,  G09G2300/0861 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08

Abstract: A gate driver IC (i.e., gate driver circuit), when set to a first mode by a logic signal of the terminal FNC*, shifts data in the gate driver IC in synchronization with one clock cycle of a clock inputted to the terminal CLK** (clock input terminal), and outputs a selection voltage or a non-selection voltage based on a data position in the gate driver IC; and when set to a second mode by a logic signal of the tenninal FNC*, shifts data in the gate driver IC in synchronization with n clock cycles (n is an integer of at least 2) of a clock inputted to the terminal CLK**, and outputs the selection voltage or the non-selection voltage based on the data position in the gate driver IC.

Abstract translation: 栅极驱动器IC（即栅极驱动器电路）当通过端子FNC *的逻辑信号设置为第一模式时，与输入到端子CLK *的时钟的一个时钟周期同步地移位栅极驱动器IC中的数据。 *（时钟输入端子），并且基于栅极驱动器IC中的数据位置输出选择电压或非选择电压; 并且当通过终端FNC *的逻辑信号设置为第二模式时，与输入到端子CLK **的时钟的n个时钟周期（n为至少为2的整数）同步地移位栅极驱动器IC中的数据 ，并且基于栅极驱动器IC中的数据位置输出选择电压或非选择电压。

公开(公告)号：US20160163264A1

公开(公告)日：2016-06-09

申请号：US14904741

申请日：2014-06-12

Applicant: JOLED INC.

Inventor： Masaru NISHIMURA ,  Toshiyuki KATO ,  Hirofumi NAKAGAWA

IPC: G09G3/32

CPC classification number: G09G3/3258 ,  G09G3/3266 ,  G09G2300/0871 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/068 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2320/041 ,  G09G2330/045 ,  G09G2330/08 ,  H05B33/08 ,  Y02B20/32

Abstract: An EL display apparatus includes: gate driver ICs (i. e., gate driver circuits); a plurality of pixels; gate signal lines each transmit a selection voltage for selecting a pixel from the pixels and non-selection voltage for placing a pixel in a non-selection state; and TCON. The pixels each include: a driving transistor; an EL element; a first switching transistor; and a second switching transistor. The gate driver ICs each include scanning and outputting buffer circuits which are connected to TCON to which an output signal of each of the scanning and outputting buffer circuits is inputted.

Abstract translation: EL显示装置包括：栅极驱动器IC（即栅极驱动电路）; 多个像素; 栅极信号线各自从像素发送用于选择像素的选择电压和用于将像素置于非选择状态的非选择电压; 和TCON。 各像素包括：驱动晶体管; EL元素; 第一开关晶体管; 和第二开关晶体管。 栅极驱动器IC各自包括扫描和输出缓冲器电路，其连接到TCON，每个扫描和输出缓冲器电路的输出信号被输入到TCON。