Invention Application
- Patent Title: ERROR HANDLING IN TRANSACTIONAL BUFFERED MEMORY
- Patent Title (中): 在交易缓冲存储器中的错误处理
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Application No.: US14578413Application Date: 2014-12-20
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Publication No.: US20160179610A1Publication Date: 2016-06-23
- Inventor: Brian S. Morris , Bill Nale , Robert G. Blankenship , Eric L. Hendrickson
- Applicant: Intel Corporation
- Main IPC: G06F11/08
- IPC: G06F11/08 ; G06F11/16
Abstract:
Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.
Public/Granted literature
- US09632862B2 Error handling in transactional buffered memory Public/Granted day:2017-04-25
Information query
