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    Refresh command control for host assist of row hammer mitigation
    2.
    发明授权
    Refresh command control for host assist of row hammer mitigation 有权

    公开(公告)号：US10950288B2

    公开(公告)日：2021-03-16

    申请号：US16370578

    申请日：2019-03-29

    申请人： Intel Corporation

    发明人： Bill Nale ,  Christopher E. Cox

    IPC分类号： G11C11/406 ,  G11C11/4096 ,  G06F3/06

    摘要： A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

    EARLY IDENTIFICATION IN TRANSACTIONAL BUFFERED MEMORY
    8.
    发明申请
    EARLY IDENTIFICATION IN TRANSACTIONAL BUFFERED MEMORY 有权
    早期识别在交易缓冲存储器

    公开(公告)号：US20160179718A1

    公开(公告)日：2016-06-23

    申请号：US14578407

    申请日：2014-12-20

    申请人： Intel Corporation

    发明人： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

    IPC分类号： G06F13/28 ,  G06F13/42

    CPC分类号： G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

    摘要： A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

    摘要翻译： 读取返回序列将通过事务缓冲存储器接口发送到主机设备，其中序列至少包括对第一读取请求的第一读取返回和第二读取返回到第二读取请求。 在第一读取返回中编码第二读取返回的跟踪器标识符，并且将第一读取返回与第二读取返回的跟踪器标识符一起发送到主机设备。 在发送第一次读取返回后，第二个读取返回被发送到主机设备。

    Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth
    10.
    发明授权
    Synchronous dynamic random access memory (SDRAM) dual in-line memory module (DIMM) having increased per data pin bandwidth 有权

    公开(公告)号：US11699471B2

    公开(公告)日：2023-07-11

    申请号：US17030107

    申请日：2020-09-23

    申请人： Intel Corporation

    发明人： Duane E. Galbi ,  Bill Nale

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G06F13/28 ,  G11C8/18

    CPC分类号： G11C7/222 ,  G06F13/1684 ,  G06F13/287 ,  G11C7/1012 ,  G11C8/18

    摘要： An apparatus is described. The apparatus includes logic circuitry to multiplex on a data bus a first data burst, a second data burst, a third data burst and a fourth data burst having different respective base target addresses that respectively target a first memory rank, a second memory rank, a third memory rank and a fourth memory rank. A first data transfer for the first data burst occurs on a first edge of a first pulse of a data strobe signal for the data bus and a second data transfer for the second data burst occurs on a second edge of the first pulse of the data strobe signal. A third data transfer for the third data burst occurs on a first edge of a second pulse of the data strobe signal for the data bus and a fourth data transfer for the fourth data burst occurs on a second edge of the second pulse. The second pulse immediately follows the first pulse on the data strobe signal. The first memory rank, the second memory rank, the third memory rank and the fourth memory rank are on a same memory module.