Invention Application
US20160204002A1 Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects
审中-公开
用于后端(BEOL)互连的自对准通孔和插头图案
- Patent Title: Self-Aligned Via and Plug Patterning for Back End of Line (BEOL) Interconnects
- Patent Title (中): 用于后端(BEOL)互连的自对准通孔和插头图案
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Application No.: US14914095Application Date: 2013-09-27
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Publication No.: US20160204002A1Publication Date: 2016-07-14
- Inventor: CHARLES H. WALLACE , PAUL A. NYHUS
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- International Application: PCT/US13/62323 WO 20130927
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L21/764 ; H01L23/498

Abstract:
Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line having alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure. Each dielectric line of the grating of the second structure has a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.
Public/Granted literature
- US09666451B2 Self-aligned via and plug patterning for back end of line (BEOL) interconnects Public/Granted day:2017-05-30
Information query
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