发明申请
US20160204037A1 INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON
有权
集成具有选择性外延生长和制造设备的VLSI兼容FIN结构
- 专利标题： INTEGRATING VLSI-COMPATIBLE FIN STRUCTURES WITH SELECTIVE EPITAXIAL GROWTH AND FABRICATING DEVICES THEREON
- 专利标题（中）： 集成具有选择性外延生长和制造设备的VLSI兼容FIN结构
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申请号： US14777736申请日： 2013-06-28
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公开(公告)号： US20160204037A1公开(公告)日： 2016-07-14
- 发明人: Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
- 申请人： Niti Goel , Ravi Pillarisetty , Willy Rachmady , Jack T. Kavalieros , Gilbert Dewey , Benjamin Chu-Kung , Marko Radosavljevic , Matthew V. Metz , Niloy Mukherjee , Robert S. Chau
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 国际申请： PCT/US2013/048773 WO 20130628
- 主分类号： H01L21/8238
- IPC分类号： H01L21/8238 ; H01L21/762 ; H01L21/02
摘要：
Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom of first trenches formed between shallow trench isolation (STI) regions. The STI regions and first trench heights are at least 1.5 times their width. The STI regions are etched away to expose the top surface of the substrate to form second trenches between the first epitaxial regions. A layer of a spacer material is formed in the second trenches on sidewalls of the first epitaxial regions. Second epitaxial regions of a second type material are grown from the substrate surface at a bottom of the second trenches between the first epitaxial regions. Pairs of n- and p-type fins can be formed from the first and second epitaxial regions. The fins are co-integrated and have reduced defects from material interface lattice mismatch.
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