Invention Application
US20160225768A1 III-V CMOS INTEGRATION ON SILICON SUBSTRATE VIA EMBEDDED GERMANIUM-CONTAINING LAYER
有权
通过嵌入式锗含量层的硅基底层III-V CMOS集成
- Patent Title: III-V CMOS INTEGRATION ON SILICON SUBSTRATE VIA EMBEDDED GERMANIUM-CONTAINING LAYER
- Patent Title (中): 通过嵌入式锗含量层的硅基底层III-V CMOS集成
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Application No.: US14609507Application Date: 2015-01-30
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Publication No.: US20160225768A1Publication Date: 2016-08-04
- Inventor: Cheng-Wei Cheng , Devendra K. Sadana , Kuen-Ting Shiu
- Applicant: International Business Machines Corporation
- Main IPC: H01L27/092
- IPC: H01L27/092 ; H01L21/8252 ; H01L29/32 ; H01L21/02 ; H01L27/12 ; H01L29/205

Abstract:
After forming a first trench and a second trench extending through a top elemental semiconductor layer present on a substrate including, from bottom to top, a handle substrate, a compound semiconductor template layer and a buried insulator layer to define a top elemental semiconductor layer portion for a p-type metal-oxide-semiconductor transistor, the second trench is vertically expanded through the buried insulator layer to provide an expanded second trench that exposes a top surface of the compound semiconductor template layer at a bottom of the expanded second trench. A stack of a compound semiconductor buffer layer and a top compound semiconductor layer is epitaxially grown on the compound semiconductor template layer within the expanded second trench for an n-type metal-oxide-semiconductor transistor.
Public/Granted literature
- US09412744B1 III-V CMOS integration on silicon substrate via embedded germanium-containing layer Public/Granted day:2016-08-09
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