- 专利标题: Method for Via Plating with Seed Layer
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申请号: US15138033申请日: 2016-04-25
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公开(公告)号: US20160240434A1公开(公告)日: 2016-08-18
- 发明人: Shin-Yi Yang , Ching-Fu Yeh , Tz-Jun Kuo , Hsiang-Huan Lee , Ming-Han Lee
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号: H01L21/768
- IPC分类号: H01L21/768
摘要:
Presented herein is a method for plating comprising providing a substrate having a dielectric layer formed over a trace, and forming a via/trench opening extending through the dielectric layer, the via/trench opening exposing a surface of the trace. The method further comprises forming a seed layer in the via/trench opening and contacting the trace and forming a protection layer over the seed layer. The protection layer is removed and a conductive layer deposited on the seed layer in a single plating process step by applying a plating solution in the via/trench opening.
公开/授权文献
- US09640431B2 Method for via plating with seed layer 公开/授权日:2017-05-02
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