公开(公告)号：US20220359483A1

公开(公告)日：2022-11-10

申请号：US17474461

申请日：2021-09-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Han-Tang Hung ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L25/18 ,  H01L23/31 ,  H01L23/485 ,  H01L23/00 ,  H01L23/58 ,  H01L21/78 ,  H01L25/00

摘要： Embodiments of the present disclosure provide a semiconductor package comprising a first integrated circuit (IC) die having a first back-end-of-the-line (BEOL) structure, a second integrated circuit die having a second BEOL structure, an integrated BEOL structure having a first side in direct contact with both the first BEOL structure and the second BEOL structure. In some embodiments, a substrate is further disposed at a second side of the integrated BEOL structure to support both the first integrated circuit die and the second integrated circuit die.

公开(公告)号：US09548241B2

公开(公告)日：2017-01-17

申请号：US15056872

申请日：2016-02-29

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Huan Lee ,  Shau-Lin Shue ,  Keith Kuang-Kuo Koai ,  Hai-Ching Chen ,  Tung-Ching Tseng ,  Wen-Cheng Yang ,  Chung-En Kao ,  Ming-Han Lee ,  Hsin-Yen Huang

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/677 ,  H01L21/67 ,  H01L21/285 ,  H01L21/321

CPC分类号： H01L21/76846 ,  H01L21/02057 ,  H01L21/0206 ,  H01L21/02063 ,  H01L21/02631 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/3212 ,  H01L21/67184 ,  H01L21/67207 ,  H01L21/677 ,  H01L21/67742 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/7684 ,  H01L21/76862 ,  H01L21/76871 ,  H01L21/76877

摘要： Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

摘要翻译： 公开了半导体器件金属化系统和方法。 在一些实施例中，用于半导体器件的金属化系统包括主机以及靠近主机设置的多个模块。 多个模块中的一个模块包括物理气相沉积（PVD）模块，并且多个模块中的一个模块包括紫外线（UV）固化模块。

公开(公告)号：US20160005648A1

公开(公告)日：2016-01-07

申请号：US14853104

申请日：2015-09-14

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shin-Yi Yang ,  Hsiang-Huan Lee ,  Ming-Han Lee ,  Ching-Fu Yeh ,  Pei-Yin Liou

IPC分类号： H01L21/768

CPC分类号： H01L21/76847 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53276 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device may include: forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. The method may further include the step of catalytically growing a graphene layer on an exposed surface of the metal line, and depositing an amorphous carbon layer on sidewalls of the opening. The steps of catalytically growing the graphene layer and depositing the amorphous carbon layer may be performed simultaneously.

摘要翻译： 形成器件的方法可以包括：通过电介质层和下面的蚀刻停止层形成开口以暴露金属线。 该方法还可以包括在金属线的暴露表面上催化生长石墨烯层并在开口的侧壁上沉积无定形碳层的步骤。 催化生长石墨烯层和沉积非晶碳层的步骤可以同时进行。

公开(公告)号：US20230042548A1

公开(公告)日：2023-02-09

申请号：US17394622

申请日：2021-08-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/50 ,  H01L23/528 ,  H01L23/522 ,  H01L27/088 ,  H01L21/8234

摘要： The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The stack of channel structures and the gate structure are between the first and second source/drain structures. The gate structure surrounds the stack of channel structures. A first conductive wire overlies and is spaced from the semiconductor device. The first conductive wire includes a first stack of conductive layers. A first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. The first conductive contact is on a back-side of the first source/drain structure.

公开(公告)号：US10163786B2

公开(公告)日：2018-12-25

申请号：US15458078

申请日：2017-03-14

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Tz-Jun Kuo

IPC分类号： H01L23/48 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L29/423

摘要： A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.

公开(公告)号：US09818644B2

公开(公告)日：2017-11-14

申请号：US15088134

申请日：2016-04-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Shin-Yi Yang ,  Hsi-Wen Tien ,  Ming-Han Lee ,  Hsiang-Huan Lee ,  Shau-Lin Shue

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522 ,  H01L21/285

CPC分类号： H01L21/76879 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76876 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

公开(公告)号：US09490205B2

公开(公告)日：2016-11-08

申请号：US14713179

申请日：2015-05-15

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Tsung-Jung Tsai ,  Hsiang-Huan Lee ,  Ming-Han Lee

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/00 ,  H01L2924/0002

摘要： A copper alloy layer is blanket deposited over a low k dielectric layer and in via openings within the low k dielectric layer. The blanket deposited layer is then anisotropically etch to form horizontal interconnects. The interconnects are annealed to form a metal oxide barrier lining. A second low k dielectric layer is then depositing over the horizontal interconnects. Air gaps can be formed between adjacent interconnects to lower parasitic capacitance therebetween.

公开(公告)号：US11640940B2

公开(公告)日：2023-05-02

申请号：US17314269

申请日：2021-05-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Wei Li ,  Yu-Chen Chan ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L23/532

摘要： An interconnection structure, along with methods of forming such, are described. The interconnection structure includes a first portion of a conductive layer, and the conductive layer includes one or more graphene layers. The first portion of the conductive layer includes a first interface portion and a second interface portion opposite the first interface portion, and each of the first and second interface portion includes a metal disposed between adjacent graphene layers. The structure further includes a second portion of the conductive layer disposed adjacent the first portion of the conductive layer, and the second portion of the conductive layer includes a third interface portion and a fourth interface portion opposite the third interface portion. Each of the third and fourth interface portion includes the metal disposed between adjacent graphene layers. The structure further includes a dielectric material disposed between the first and second portions of the conductive layer.

公开(公告)号：US20220415798A1

公开(公告)日：2022-12-29

申请号：US17355566

申请日：2021-06-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Wei Li ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L23/535 ,  H01L21/02 ,  H01L21/768

摘要： The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

公开(公告)号：US11482451B2

公开(公告)日：2022-10-25

申请号：US16949953

申请日：2020-11-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guanyu Luo ,  Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45 ,  H01L23/522

摘要： A method includes receiving an integrated circuit (IC) layout having a plurality of metal features in a metal layer. The method also includes classifying the plurality of metal features into a first type of metal features and a second type of metal features based on a dimensional criterion, where the first type of the metal features have dimensions greater than the second type of the metal features. The method further includes assigning to the first type of metal features a first metal material, and to the second type of metal features a second metal material, where the second metal material is different from the first metal material. The method additionally includes forming the plurality of metal features embedded within a dielectric layer, where each of the plurality of metal features have the respective assigned metal materials.