This present invention provides a chip scale sensing chip package, comprising a sensing chip having a first top surface and a first bottom surface opposite to the first top surface, which comprises a sensing device near the first top surface, a plurality of conductive pads near the first top surface and adjacent to the sensing device; a plurality of through holes on the first top surface and each of the through holes exposing one of the conductive pads corresponding to with each other; a plurality of conductive structure formed on the first bottom surface; and a re-distribution layer (RDL) formed on the first bottom surface and the first through holes to respectively connect to each of the conductive pads and each of the conductive structures; a spacing layer, surrounding the sensing chip, formed on the sensing chip. The spacing layer has a second top surface, a second bottom surface and an opening through the second top surface and the second bottom surface, wherein the opening corresponds to the sensing device and the inner wall of the opening remains a desired distance d (d>0) with the sensing device; and a first adhesive layer sandwiched between the second bottom surface of the spacing layer and the first top surface of the sensing chip.