Invention Application
- Patent Title: SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
- Patent Title (中): 半导体器件及制造半导体器件的方法
-
Application No.: US15076753Application Date: 2016-03-22
-
Publication No.: US20160293709A1Publication Date: 2016-10-06
- Inventor: Tatsuo NAKAYAMA , Hironobu MIYAMOTO
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Priority: JP2015-070738 20150331
- Main IPC: H01L29/201
- IPC: H01L29/201 ; H01L21/768 ; H01L29/423 ; H01L23/535 ; H01L29/78 ; H01L29/66

Abstract:
Characteristics of a semiconductor device are improved. A semiconductor device includes a voltage clamp layer, a channel base layer, a channel layer, and a barrier layer on a substrate. A trench extends to a certain depth of the channel layer through the barrier layer. A gate electrode is disposed on a gate insulating film within the trench. A source electrode and a drain electrode are provided on the two respective sides of the gate electrode. A coupling within a through-hole that extends to the voltage clamp layer electrically couples the voltage clamp layer to the source electrode. An impurity region containing an impurity having an acceptor level deeper than that of a p-type impurity is provided under the through-hole. The voltage clamp layer decreases variations in characteristics such as threshold voltage and on resistance. The contact resistance is reduced through hopping conduction due to the impurity in the impurity region.
Public/Granted literature
- US09978642B2 III-V nitride semiconductor device having reduced contact resistance Public/Granted day:2018-05-22
Information query
IPC分类: