- 专利标题: POWER EFFICIENT PROCESSOR ARCHITECTURE
-
申请号: US15192134申请日: 2016-06-24
-
公开(公告)号: US20160306415A1公开(公告)日: 2016-10-20
- 发明人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
- 申请人: Andrew J. Herdrich , Rameshkumar G. Illikkal , Ravishankar Iyer , Sadagopan Srinivasan , Jaideep Moses , Srihari Makineni
- 主分类号: G06F1/32
- IPC分类号: G06F1/32 ; G06F12/08
摘要:
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.
公开/授权文献
- US09870047B2 Power efficient processor architecture 公开/授权日:2018-01-16
信息查询