Invention Application
US20160307850A1 OVERLAY MARKS AND SEMICONDUCTOR PROCESS USING THE OVERLAY MARKS
有权
使用覆盖标志的覆盖标记和半导体工艺
- Patent Title: OVERLAY MARKS AND SEMICONDUCTOR PROCESS USING THE OVERLAY MARKS
- Patent Title (中): 使用覆盖标志的覆盖标记和半导体工艺
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Application No.: US14687912Application Date: 2015-04-15
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Publication No.: US20160307850A1Publication Date: 2016-10-20
- Inventor: Chia-Ching Lin , En-Chiuan Liou , Chia-Hung Wang , Sho-Shen Lee
- Applicant: United Microelectronics Corp.
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L29/78
Abstract:
An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.
Public/Granted literature
- US09490217B1 Overlay marks and semiconductor process using the overlay marks Public/Granted day:2016-11-08
Information query
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