公开(公告)号：US09583568B2

公开(公告)日：2017-02-28

申请号：US14612300

申请日：2015-02-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/66 ,  H01L21/84 ,  H01L27/06 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US20240387239A1

公开(公告)日：2024-11-21

申请号：US18209488

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Tsang Chen ,  Chia-Ching Lin ,  Wen-Liang Huang

IPC: H01L21/762 ,  H01L21/8234 ,  H01L29/66

Abstract: A manufacturing method of a semiconductor structure includes the following steps. Fin-shaped structures are formed by patterning a first region of a semiconductor substrate. A first shallow trench is formed in a second region of the semiconductor substrate. A part of the semiconductor substrate is exposed by a bottom of the first shallow trench. A first etching process is performed. At least a part of one of the fin-shaped structures is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench. The manufacturing method of the present invention may be used to achieve the purposes of process simplification and/or manufacturing cost reduction.

公开(公告)号：US09490217B1

公开(公告)日：2016-11-08

申请号：US14687912

申请日：2015-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Lin ,  En-Chiuan Liou ,  Chia-Hung Wang ,  Sho-Shen Lee

IPC: H01L23/544 ,  H01L21/68 ,  H01L29/78

CPC classification number: H01L29/785 ,  G03F7/70633 ,  G03F7/70683

Abstract: An overlay mark for determining the alignment between two separately generated patterns formed along with two successive layers above a substrate is provided in the present invention, wherein both the substrate and the overlay mark include at least two pattern zones having periodic structures with different orientations, and the periodic structures of the overlay mark are orthogonally overlapped with the periodic structures of the substrate.

Abstract translation: 在本发明中提供了用于确定在衬底上方与两个连续层形成的两个单独产生的图案之间的对准的覆盖标记，其中衬底和覆盖标记都包括具有不同取向的周期性结构的至少两个图案区域，以及 覆盖标记的周期性结构与衬底的周期性结构正交地重叠。

公开(公告)号：US09837282B1

公开(公告)日：2017-12-05

申请号：US15667641

申请日：2017-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen ,  En-Chiuan Liou

IPC: H01L21/02 ,  H01L21/308 ,  H01L21/66 ,  H01L21/762 ,  H01L29/66

CPC classification number: H01L22/12 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.

公开(公告)号：US09761460B1

公开(公告)日：2017-09-12

申请号：US15365967

申请日：2016-12-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen ,  En-Chiuan Liou

IPC: H01L21/02 ,  H01L21/308 ,  H01L29/66 ,  H01L21/762 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/3083 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.

公开(公告)号：US09568842B2

公开(公告)日：2017-02-14

申请号：US14696488

申请日：2015-04-27

Applicant: UNITED MiCROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Chia-Ching Lin ,  Yi-Jing Wang

IPC: B25H7/04 ,  B41M5/00 ,  G03F7/20 ,  G03F1/70

CPC classification number: G03F7/70633 ,  G03F1/70

Abstract: An overlay operation method and an overlay control method are disclosed. A first mark and a second mark are identified on a substrate, wherein the first mark and the second mark are formed by a process in combination with using a photomask. Next, a first measurement is performed to obtain an offset between the first mark and the second mark in a direction. Then, an operation is performed to judge whether the offset is in a range from a pre-determined offset minus a deviation to the pre-determined offset plus the deviation, wherein the pre-determined offset is determined by the photomask.

Abstract translation: 公开了覆盖操作方法和覆盖控制方法。 在基板上识别第一标记和第二标记，其中第一标记和第二标记通过与使用光掩模组合的方法形成。 接下来，执行第一测量以在方向上获得第一标记和第二标记之间的偏移。 然后，执行操作以判断偏移是否在从预定偏移减去偏差到预定偏移加上偏差的范围内，其中预定偏移由光掩模确定。

公开(公告)号：US20160204197A1

公开(公告)日：2016-07-14

申请号：US14612300

申请日：2015-02-03

Applicant: United Microelectronics Corp.

Inventor： En-Chiuan Liou ,  Ssu-I Fu ,  Chia-Lin Lu ,  Shih-Hung Tsai ,  Chih-Wei Yang ,  Chia-Ching Lin ,  Chia-Hsun Tseng ,  Rai-Min Huang

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0684 ,  H01L21/76 ,  H01L21/762 ,  H01L21/76232 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7846 ,  H01L29/7851

Abstract: The present invention provides a semiconductor structure, including a substrate, a shallow trench isolation (STI) disposed in the substrate, a plurality of first fin structures disposed in the substrate, where each first fin structure and the substrate have same material, and a plurality of second fin structures disposed in the STI, where each second fin structure and the STI have same material.

Abstract translation: 本发明提供一种半导体结构，包括基板，设置在基板中的浅沟槽隔离（STI），设置在基板中的多个第一翅片结构，其中每个第一翅片结构和基板具有相同的材料，以及多个 设置在STI中的第二鳍结构，其中每个第二鳍结构和STI具有相同的材料。

公开(公告)号：US09007571B2

公开(公告)日：2015-04-14

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G01N21/00 ,  G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US20150055125A1

公开(公告)日：2015-02-26

申请号：US13971776

申请日：2013-08-20

Applicant: United Microelectronics Corp.

Inventor： Wei-Jhe Tzai ,  Kuei-Chun Hung ,  Chun-Chi Yu ,  Chien-Hao Chen ,  Chia-Ching Lin

IPC: G03F9/00

CPC classification number: G03F7/70633

Abstract: A measurement method of an overlay mark is provided. An overlay mark on a wafer is measured with a plurality of different wavelength regions of an optical measurement tool, so as to obtain a plurality of overlay values corresponding to the wavelength regions. The overlay mark on the wafer is measured with an electrical measurement tool to obtain a reference overlay value. The wavelength region that corresponds to the overlay value closest to the reference overlay value is determined as a correct wavelength region for the overlay mark.

Abstract translation: 提供重叠标记的测量方法。 用光学测量工具的多个不同波长区域测量晶片上的覆盖标记，以便获得对应于波长区域的多个覆盖值。 用电测量工具测量晶片上的覆盖标记以获得参考覆盖值。 对应于最接近参考叠加值的覆盖值的波长区域被确定为覆盖标记的正确波长区域。

公开(公告)号：US10395999B1

公开(公告)日：2019-08-27

申请号：US15981053

申请日：2018-05-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Cheng-Hao Yang ,  En-Chiuan Liou ,  Hsiao-Lin Hsu ,  Tang-Chun Weng ,  Chia-Ching Lin ,  Yen-Pu Chen

IPC: H01L21/308 ,  H01L27/02 ,  H01L21/66 ,  H01L29/66

Abstract: A method for monitoring fin removal includes providing a substrate having a first region with first fins extending along a first direction and a second region with second fins extending along a second direction, wherein the first direction is perpendicular to the second direction; forming a material layer on the substrate to cover the first fins and the second fins; identically patterning the first fins and the second fins using a first pattern and a second pattern respectively for simultaneously removing parts of the first and second fins, thereby forming first fin features in the first region and second fin features in the second region, wherein the first pattern has a first dimension along the second direction, the second pattern has a second dimension along the second direction, and the second dimension is equal to the first dimension; and monitoring the first fin features using the second fin features.