发明申请
US20160328233A1 PACKED FINITE IMPULSE RESPONSE (FIR) FILTER PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
有权
包装有限冲突响应（FIR）过滤器，方法，系统和说明
- 专利标题： PACKED FINITE IMPULSE RESPONSE (FIR) FILTER PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
- 专利标题（中）： 包装有限冲突响应（FIR）过滤器，方法，系统和说明
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申请号： US14704633申请日： 2015-05-05
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公开(公告)号： US20160328233A1公开(公告)日： 2016-11-10
- 发明人: Edwin Jan Van Dalen , Martinus C. Wezelenburg , Steven Roos , Edward T. Grochowski , Moshe Maor
- 申请人： INTEL CORPORATION
- 申请人地址： US CA Santa Clara
- 专利权人： INTEL CORPORATION
- 当前专利权人： INTEL CORPORATION
- 当前专利权人地址： US CA Santa Clara
- 主分类号： G06F9/30
- IPC分类号： G06F9/30 ; H03H17/02
摘要：
A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.
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