公开(公告)号：US20160357563A1

公开(公告)日：2016-12-08

申请号：US14728693

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Edwin Jan Van Dalen ,  Alexander Augusteijn ,  Martinus C. Wezelenburg ,  Steven Roos

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/3016

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

Abstract translation: 处理器包括用于解码打包数据对齐加计算指令的解码单元。 指令是指示要包括第一数据元素的一个或多个源打包数据操作数的第一组，包括第二数据元素的一个或多个源压缩数据操作数的第二组，至少一个数据元偏移量。 响应于该指令，执行单元将存储结果打包数据操作数，该结果打包数据操作数包括结果数据元素，每个结果数据元素具有使用第一组源打包数据操作数的一对数据元素执行的操作值 以及第二组源打包数据操作数的数据元素。 所述执行单元将所述至少一个数据元素偏移应用于所述第一和第二组源打包数据操作数中的至少相应的一个。 所述至少一个数据元素偏移是抵消在第一和第二组源打包数据操作数中的每对数据元素之间的任何对应关系的缺乏。

公开(公告)号：US10936312B2

公开(公告)日：2021-03-02

申请号：US15947622

申请日：2018-04-06

Applicant: Intel Corporation

Inventor： Edwin Jan Van Dalen ,  Alexander Augusteijn ,  Martinus C. Wezelenburg ,  Steven Roos

IPC: G06F9/30

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

公开(公告)号：US09898286B2

公开(公告)日：2018-02-20

申请号：US14704633

申请日：2015-05-05

Applicant: INTEL CORPORATION

Inventor： Edwin Jan Van Dalen ,  Martinus C. Wezelenburg ,  Steven Roos ,  Edward T. Grochowski ,  Moshe Maor

IPC: G06F7/38 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455 ,  H03H17/02 ,  H03H17/06

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3893 ,  G06F9/455 ,  H03H17/0202 ,  H03H17/06 ,  H03H2017/0298

Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

公开(公告)号：US10001995B2

公开(公告)日：2018-06-19

申请号：US14728693

申请日：2015-06-02

Applicant: Intel Corporation

Inventor： Edwin Jan Van Dalen ,  Alexander Augusteijn ,  Martinus C. Wezelenburg ,  Steven Roos

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30032 ,  G06F9/3016

Abstract: A processor includes a decode unit to decode a packed data alignment plus compute instruction. The instruction is to indicate a first set of one or more source packed data operands that is to include first data elements, a second set of one or more source packed data operands that is to include second data elements, at least one data element offset. An execution unit, in response to the instruction, is to store a result packed data operand that is to include result data elements that each have a value of an operation performed with a pair of a data element of the first set of source packed data operands and a data element of the second set of source packed data operands. The execution unit is to apply the at least one data element offset to at least a corresponding one of the first and second sets of source packed data operands. The at least one data element offset is to counteract any lack of correspondence between the data elements of each pair in the first and second sets of source packed data operands.

公开(公告)号：US20160328233A1

公开(公告)日：2016-11-10

申请号：US14704633

申请日：2015-05-05

Applicant: INTEL CORPORATION

Inventor： Edwin Jan Van Dalen ,  Martinus C. Wezelenburg ,  Steven Roos ,  Edward T. Grochowski ,  Moshe Maor

IPC: G06F9/30 ,  H03H17/02

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/3893 ,  G06F9/455 ,  H03H17/0202 ,  H03H17/06 ,  H03H2017/0298

Abstract: A processor includes a decode unit to decode a packed finite impulse response (FIR) filter instruction that indicates one or more source packed data operands, a plurality of FIR filter coefficients, and a destination storage location. The source operand(s) include a first number of data elements and a second number of additional data elements. The second number is one less than a number of FIR filter taps. An execution unit, in response to the packed FIR filter instruction being decoded, is to store a result packed data operand. The result packed data operand includes the first number of FIR filtered data elements that each is to be based on a combination of products of the plurality of FIR filter coefficients and a different corresponding set of data elements from the one or more source packed data operands, which is equal in number to the number of FIR filter taps.

Abstract translation: 处理器包括解码单元，用于解码指示一个或多个源打包数据操作数，多个FIR滤波器系数和目的地存储位置的压缩有限脉冲响应（FIR）滤波器指令。 源操作数包括第一数量的数据元素和第二数量的附加数据元素。 第二个数字是少于FIR滤波器抽头的数量。 响应于被解码的打包FIR滤波器指令，执行单元是存储结果打包数据操作数。 结果打包数据操作数包括第一数量的FIR滤波数据元素，每个FIR滤波数据元素将基于多个FIR滤波器系数的乘积和来自一个或多个源打包数据操作数的不同对应的数据元素的组合， 其数量与FIR滤波器抽头的数量相等。