Invention Application
- Patent Title: DATA ON CLOCK LANE OF SOURCE SYNCHRONOUS LINKS
- Patent Title (中): 源码同步链路时钟数据
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Application No.: US14788721Application Date: 2015-06-30
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Publication No.: US20170005780A1Publication Date: 2017-01-05
- Inventor: Tapas Nandy , Nitin Gupta
- Applicant: STMicroelectronics International N.V.
- Main IPC: H04L7/00
- IPC: H04L7/00

Abstract:
A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
Public/Granted literature
- US09794054B2 Data on clock lane of source synchronous links Public/Granted day:2017-10-17
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