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1.发明申请公开(公告)号：US20190288693A1
公开(公告)日：2019-09-19
申请号：US15924584
申请日：2018-03-19
发明人： Nitin Gupta , Jeet Narayan Tiwari
摘要： Disclosed is a method of locking a locked loop quickly, including receiving an input signal having an input frequency, and generating an intermediate signal having an intermediate frequency intended to be equal to a geometric mean of the input frequency and a desired frequency, but not equal. Results of division of the desired output frequency by the intermediate frequency are estimated, producing a first divider value. A first locked loop utilizing a controllable oscillator is activated. A divider value of the first locked loop is set to the first divider value, and the intermediate signal is provided to the first locked loop, so that when the first locked loop reaches lock, the controllable oscillator produces the desired frequency. When the first locked loop reaches lock, a second locked loop that utilizes the controllable oscillator is activated, the first locked loop is deactivated, and generation of the intermediate signal is ceased.
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公开(公告)号：US10198014B2
公开(公告)日：2019-02-05
申请号：US15475266
申请日：2017-03-31
发明人： Kapil Kumar Tyagi , Nitin Gupta
摘要： A low dropout regulator produces output at an intermediate node. A resistive divider is coupled between the intermediate node and ground and provides a feedback signal to the low dropout regulator. A transistor has a first conduction terminal coupled to the intermediate node and a second conduction terminal coupled to an output node. A first impedance is coupled to the output node, a first switch selectively couples the first impedance to a supply node, a second impedance coupled to the output node, and a second switch selectively couples the second impedance to a ground node. Control circuitry is coupled to the control terminal of the transistor and to control terminals of the first and second switches. The control circuitry switches the electronic device to a power down mode by turning off transistor, closing the first and second switches, and turning off the low dropout regulator.
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公开(公告)号：US20180287617A1
公开(公告)日：2018-10-04
申请号：US15475274
申请日：2017-03-31
发明人： Anand Kumar , Nitin Gupta , Nitin Jain
摘要： An electronic device disclosed herein includes a locked loop circuit configured to receive a reference signal intended to have an intended frequency, wherein the locked look circuit is intended to generate an intended output signal having an intended frequency equal to the intended frequency multiplied by an intended multiplier. A frequency counter counts a number of pulses of the reference signal during a time window so as to determine an actual frequency of the reference signal. A control circuit determines an actual multiplier for the locked loop circuit that, when multiplied by the actual frequency of the reference signal, causes the locked loop circuit to generate an actual output signal having an actual frequency equal to the intended frequency.
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公开(公告)号：US20180109266A1
公开(公告)日：2018-04-19
申请号：US15297537
申请日：2016-10-19
发明人： Nitin Gupta , Jeet Narayan Tiwari
CPC分类号： H03L7/1974 , H03K19/20 , H03K21/00 , H03K21/10 , H03K23/00 , H03K23/667 , H03K23/68 , H03K23/70
摘要： In accordance with an embodiment, a circuit includes an input clock terminal, an output clock terminal, a first input data terminal, and a set of input data terminals having a number of terminals. A divide-by-two block is coupled to the output clock terminal. A modular one-shot clock divider is coupled between the input clock terminal and the divide-by-two block. The modular one-shot clock divider is further coupled to the set of input data terminals. An intermediate clock generation block is coupled between the input clock terminal and the modular one-shot clock divider. The intermediate clock generation block includes a first digital logic block coupled between the input clock terminal and the modular one-shot clock divider. The first digital logic block is further coupled to the first input data terminal, and a clock-blocking block is coupled between the divide-by-two block and the first digital logic block.
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公开(公告)号：US09794054B2
公开(公告)日：2017-10-17
申请号：US14788721
申请日：2015-06-30
发明人： Tapas Nandy , Nitin Gupta
CPC分类号： H04L7/0008 , G06F1/10 , H04J3/0685 , H04L1/0026 , H04L5/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L7/0337
摘要： A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
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公开(公告)号：US09647699B1
公开(公告)日：2017-05-09
申请号：US14984040
申请日：2015-12-30
发明人： Nitin Gupta , Tapas Nandy
CPC分类号： H04B1/04 , H03F3/24 , H04B2001/0408
摘要： A power harvesting circuit for use in an open drain transmitter circuit is configured to generate two distinct harvested supply voltages at different voltage levels along with two distinct cascode voltages at different voltage levels. The harvested supply voltages are used to power circuitry in the transmitter circuit. The cascode voltages are used to bias cascode transistors in the open drain circuitry for different channels.
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7.发明授权公开(公告)号：US09000857B2
公开(公告)日：2015-04-07
申请号：US13919195
申请日：2013-06-17
发明人： Abhirup Lahiri , Nitin Gupta
CPC分类号： H03L7/085 , H03L7/0995
摘要： A circuit generates a compensation signal that can remove noise in a VCO introduced by a supply signal (i.e., supply-side noise). The circuit includes two transistors connected in series. A resistor is connected between the gate of the first transistor and the supply signal, and a capacitor is connected between the gate of the second transistor and the supply signal. The circuit is designed so that the transconductance of one transistor is greater than or equal to twice the transconductance of a second transistor. The compensation signal is supplied through a capacitor, which compensates for capacitors in a VCO, to an internal supply node of the VCO. At the internal supply node, the compensation signal removes (or greatly reduces) the noise introduced by the supply signal noise, resulting in a less-noisy output signal from the VCO.
摘要翻译： 电路产生可以去除由电源信号引入的VCO（即电源侧噪声）中的噪声的补偿信号。 该电路包括串联连接的两个晶体管。 电阻器连接在第一晶体管的栅极和电源信号之间，电容器连接在第二晶体管的栅极和电源信号之间。 该电路被设计成使得一个晶体管的跨导大于或等于第二晶体管的跨导的两倍。 补偿信号通过补偿VCO中的电容器的电容器提供给VCO的内部电源节点。 在内部电源节点，补偿信号消除（或大大降低）由电源信号噪声引入的噪声，导致VCO噪声较小的输出信号。
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公开(公告)号：US08681918B2
公开(公告)日：2014-03-25
申请号：US13784571
申请日：2013-03-04
发明人： Nitin Gupta
IPC分类号： H04L7/00
CPC分类号： H03L7/199 , H03L7/0807 , H03L7/0812 , H03L7/091 , H04L7/0337
摘要： In a method for recovery of a dock from a received digital data stream and an apparatus for recovering a clock from a received digital data stream, phase-shifted dock signals are generated from a receiver's dock. After selecting one of the phase-shifted clock signals, two other phase-shifted clock signals are determined. Depending on sample values taken at rising/falling edges of the three selected phase-shifted clock signals, counter values are increased and compared. The selection of phase-shifted clock signals and the steps of sampling the input digital data stream, comparing the values and increasing counter values, if required, are repeatedly performed until the comparison result of the counter values indicates that one of the latter determined phase-shifted clock signals strobes the received digital data stream in the center of a bit period.
摘要翻译： 在从接收到的数字数据流中恢复基座的方法以及从接收的数字数据流中恢复时钟的装置中，从接收器的基座产生相移的停靠信号。 在选择一个相移时钟信号之后，确定另外两个相移时钟信号。 根据在三个选定的相移时钟信号的上升沿/下降沿采集的采样值，增加和比较计数器值。 如果需要，相移时钟信号的选择和对输入数字数据流进行采样的步骤，比较值和增加计数器值，直到计数器值的比较结果指示后一个确定的相位时钟信号之一， 移位的时钟信号在接收到的位数周期的中心选通接收到的数字数据流。
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9.发明授权公开(公告)号：US10771073B2
公开(公告)日：2020-09-08
申请号：US16696247
申请日：2019-11-26
发明人： Nitin Gupta
摘要： An oscillator circuit powered by a source voltage generates an oscillating output signal. The oscillating output signal is level shifted and applied to a first input of a multiplexer. A second input of the multiplexer receives the oscillating output signal. The multiplexer selects one of the oscillating output signal and the level shifted oscillating output signal for output as a selected oscillating output signal in response to a select signal. A locked loop circuit generates controls a frequency of the oscillating output signal as a function of the selected oscillating output signal and a reference oscillating signal. The select signal further selects one of a reference voltage and the source voltage of the oscillator circuit as an error amplifier reference voltage for a voltage regulator circuit that generates the first power supply voltage.
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10.发明申请公开(公告)号：US20190097641A1
公开(公告)日：2019-03-28
申请号：US15718715
申请日：2017-09-28
发明人： Nitin Gupta , Ankit Gupta , Anand Kumar
摘要： Disclosed herein is a method of calibrating a voltage controlled oscillator (VCO) for a phase locked loop. The method includes prior to activating the phase locked loop, and prior to activating a frequency locked loop, causing a bias signal generator circuit to generate a control signal with a fixed control voltage for the VCO. The method continued with activating the frequency locked loop, and adjusting the bias signal generator to calibrate a transconductance of the bias signal generator while the frequency locked loop is activated. The frequency locked loop is then deactivated, and the phase locked loop is activated.
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