Invention Application
US20170024926A1 ZERO PIXEL CULLING FOR GRAPHICS PROCESSING
有权
ZERO PIXEL CULLING FOR GRAPHICAL PROCESSING
- Patent Title: ZERO PIXEL CULLING FOR GRAPHICS PROCESSING
- Patent Title (中): ZERO PIXEL CULLING FOR GRAPHICAL PROCESSING
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Application No.: US14805088Application Date: 2015-07-21
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Publication No.: US20170024926A1Publication Date: 2017-01-26
- Inventor: Nagarjuna Duvvuru , Tao Wang , Jian Liang , Chunlin Wang
- Applicant: QUALCOMM Incorporated
- Main IPC: G06T15/40
- IPC: G06T15/40 ; G06T15/00

Abstract:
A graphics processing unit (GPU) may include a triangle setup engine (TSE) configured to determine coordinates of a triangle, rotate coordinates of the triangle based on an angle. To rotate the coordinates, the TSE generates coordinates of the triangle in a rotated domain, and determines coordinates of a bounding box in the rotated domain based on the coordinates of the triangle in the rotated domain. The TSE determines a first plurality of parallel scanlines in the rotated domain, and a second plurality of parallel scanlines in the rotated domain. The first and second pluralities of scanlines are perpendicular. The TSE determines whether the bounding box coordinates are located within two adjacent scanlines. If the bounding box coordinates are located within the two adjacent scanlines, the TSE removes the triangle from the scene.
Public/Granted literature
- US09959665B2 Zero pixel culling for graphics processing Public/Granted day:2018-05-01
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