Invention Application
- Patent Title: METHODS AND STRUCTURES FOR BACK END OF LINE INTEGRATION
- Patent Title (中): 线路整合后端的方法和结构
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Application No.: US15043011Application Date: 2016-02-12
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Publication No.: US20170025347A1Publication Date: 2017-01-26
- Inventor: Sunil K. Singh , Ravi P. Srivastava , Mark A. Zaleski , Akshey Sehgal
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Main IPC: H01L23/528
- IPC: H01L23/528 ; H01L23/522 ; H01L23/532

Abstract:
Embodiments of the present invention provide a semiconductor structure for BEOL (back end of line) integration. A directed self assembly (DSA) material is deposited and annealed to form two distinct phase regions. One of the phase regions is selectively removed, and the remaining phase region serves as a mask for forming cavities in an underlying layer of metal and/or dielectric. The process is then repeated to form complex structures with patterns of metal separated by dielectric regions.
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