发明申请
US20170032075A1 System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing 有权
用于发现半导体制造的芯片设计布局中的未知问题模式的系统和方法

  • 专利标题: System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing
  • 专利标题(中): 用于发现半导体制造的芯片设计布局中的未知问题模式的系统和方法
  • 申请号: US14810428
    申请日: 2015-07-27
  • 公开(公告)号: US20170032075A1
    公开(公告)日: 2017-02-02
  • 发明人: Shauh-Teh JuangJason Zse-Cherng Lin
  • 申请人: DMO Systems Limited
  • 主分类号: G06F17/50
  • IPC分类号: G06F17/50
System And Method For Discovering Unknown Problematic Patterns In Chip Design Layout For Semiconductor Manufacturing
摘要:
A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.
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