公开(公告)号：US20180164792A1

公开(公告)日：2018-06-14

申请号：US15375186

申请日：2016-12-12

申请人： DMO Systems Limited

发明人： Jason Zse-Cherng Lin ,  Shauh-Teh Juang

IPC分类号： G05B19/418 ,  G05B13/02

CPC分类号： G05B13/0265 ,  G05B19/41875 ,  G05B2219/32199 ,  G05B2219/32205 ,  G05B2219/37224 ,  G05B2219/45031 ,  Y02P90/14 ,  Y02P90/22 ,  Y02P90/26

摘要： A system for auto defect screening using adaptive machine learning includes an adaptive model controller, a defect/nuisance library and a module for executing data modeling analytics. The adaptive model controller has a feed-forward path for receiving a plurality of defect candidates in wafer inspection, and a feedback path for receiving defects of interest already screened by one or more existing defect screening models after wafer inspection. The adaptive model controller selects data samples from the received data, interfaces with scanning electron microscope (SEM) review/inspection to acquire corresponding SEM results that validate if each data sample is a real defect or nuisance, and compiles model training and validation data. The module of executing data modeling analytics is adaptively controlled by the adaptive model controller to generate and validate one or more updated defect screening models using the model training and validation data according to a target specification.

公开(公告)号：US09547745B1

公开(公告)日：2017-01-17

申请号：US14810428

申请日：2015-07-27

申请人： DMO Systems Limited

发明人： Shauh-Teh Juang ,  Jason Zse-Cherng Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.

摘要翻译： 系统包括用于存储半导体制造中的芯片设计布局的关键签名数据库的关键签名库和用于基于存储在关键签名数据库中的已知有问题的电路图案创建统计模型的统计模型创建者，以及基于物理上的偏差的目标规范 测量和仿真数据或与已知有问题的电路图案相关联的设计数据。 该系统还具有基于统计模型的预测器，用于通过将统计模型应用于从随机布局生成器产生的大量候选电路图案中，或者基于确定的热点位置从芯片设计布局提取来预测和发现未知有问题的电路图案 通过延长光刻工艺检查芯片设计布局或使用激进的灵敏度设置检查使用芯片设计布局制造的晶圆。

公开(公告)号：US20160217240A1

公开(公告)日：2016-07-28

申请号：US14607352

申请日：2015-01-28

申请人： DMO Systems Limited

发明人： Jason Zse-Cherng Lin ,  Shauh-Teh Juang

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A hot spot methodology incorporates wafer physical measurement with digital simulation for identifying and monitoring critical hot spots. Wafer physical data are collected from the processed wafer of the semiconductor device on a plurality of target locations. Hot spot candidates and corresponding simulation data are generated by digital simulation based on models and verifications of optical proximity and lithographic process correction according to the design data of a semiconductor device. Data analytics provides data correlation between the collected wafer physical data and the simulation data. Data analytics further performs data correction on the simulation data according to the wafer physical data that have best correlation with the simulation data to better predict critical hot spots.

摘要翻译： 热点方法将晶圆物理测量与数字模拟结合起来，用于识别和监测关键热点。 在多个目标位置上从半导体器件的处理晶片收集晶片物理数据。 根据半导体器件的设计数据，通过基于光学邻近度和光刻处理校正的模型和验证的数字仿真生成热点候选和相应的仿真数据。 数据分析提供收集的晶圆物理数据和模拟数据之间的数据相关性。 数据分析还根据与仿真数据具有最佳相关性的晶圆物理数据对仿真数据进行数据校正，以更好地预测关键热点。

公开(公告)号：US08938695B1

公开(公告)日：2015-01-20

申请号：US14150772

申请日：2014-01-09

申请人： DMO Systems Limited

发明人： Shauh-Teh Juang ,  Jason Zse-Cherng Lin

IPC分类号： G06F17/50

CPC分类号： G03F7/7065 ,  G03F1/36 ,  G03F7/70441

摘要： A number of wafers of a semiconductor device are inspected to generate a plurality of wafer inspection data. A method for identifying critical hot spots to improve lithographic process of manufacturing the semiconductor device uses design signature analytics according to the plurality of wafer inspection data with reference to the design data of the semiconductor device. Design signature analytics includes global alignment, full chip pattern correlation, pattern characterization and design signature inference. The global alignment compensates for the physical coordinate offsets between the chip design data and the wafer inspection data. The full chip pattern correlation uses multi-stage pattern matching and grouping to identify highly repeating defects as hot spots. Pattern characterization extracts the design patterns and design signatures of the highly repeating defects. Design signature inference analyses the design signatures, identifies critical design signatures and determines the criticality of the critical design signatures.

摘要翻译： 检查半导体器件的多个晶片以产生多个晶片检查数据。 参考半导体器件的设计数据，用于识别关键热点以改善制造半导体器件的光刻工艺的方法使用根据多个晶片检查数据的设计签名分析。 设计签名分析包括全局对齐，全片模式相关，模式表征和设计签名推断。 全局校准补偿了芯片设计数据和晶圆检查数据之间的物理坐标偏移。 全芯片模式相关性使用多级模式匹配和分组，将高度重复的缺陷识别为热点。 模式表征提取高度重复缺陷的设计模式和设计签名。 设计签名推理分析设计签名，识别关键设计签名并确定关键设计签名的关键性。

公开(公告)号：US20140214192A1

公开(公告)日：2014-07-31

申请号：US13749682

申请日：2013-01-25

申请人： DMO SYSTEMS LIMITED

发明人： Shauh-Teh Juang ,  Jason Zse-Cherng Lin

IPC分类号： G06Q10/06

CPC分类号： H01L22/12 ,  H01L22/20

摘要： A design-based manufacturing optimization (DMO) server comprises a distributed computing system and a DMO software module incorporating with a design scanner to scan and analyze design data of a semiconductor device for optimizing manufacturing of the semiconductor device. The DMO software module sets up a pattern signature database and a manufacturing optimization database, generates design-based manufacturing recipes, interfaces with manufacturing equipment through a manufacturing interface module, and interfaces with electronic design automation suppliers for the design data through a design interface module. The DMO server executes the design-based manufacturing recipes for manufacturing optimization.

摘要翻译： 基于设计的制造优化（DMO）服务器包括分布式计算系统和与设计扫描器结合的DMO软件模块，以扫描和分析半导体器件的设计数据，以优化半导体器件的制造。 DMO软件模块设置模式签名数据库和制造优化数据库，通过制造接口模块生成基于设计的制造配方，与制造设备的接口，以及通过设计接口模块与设计数据的电子设计自动化供应商接口。 DMO服务器执行制造优化的基于设计的制造配方。

公开(公告)号：US10365617B2

公开(公告)日：2019-07-30

申请号：US15375186

申请日：2016-12-12

申请人： DMO Systems Limited

发明人： Jason Zse-Cherng Lin ,  Shauh-Teh Juang

IPC分类号： G05B19/418 ,  G05B13/02

摘要： A system for auto defect screening using adaptive machine learning includes an adaptive model controller, a defect/nuisance library and a module for executing data modeling analytics. The adaptive model controller has a feed-forward path for receiving a plurality of defect candidates in wafer inspection, and a feedback path for receiving defects of interest already screened by one or more existing defect screening models after wafer inspection. The adaptive model controller selects data samples from the received data, interfaces with scanning electron microscope (SEM) review/inspection to acquire corresponding SEM results that validate if each data sample is a real defect or nuisance, and compiles model training and validation data. The module of executing data modeling analytics is adaptively controlled by the adaptive model controller to generate and validate one or more updated defect screening models using the model training and validation data according to a target specification.

公开(公告)号：US20170032075A1

公开(公告)日：2017-02-02

申请号：US14810428

申请日：2015-07-27

申请人： DMO Systems Limited

发明人： Shauh-Teh Juang ,  Jason Zse-Cherng Lin

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A system includes a critical signature library for storing critical signature databases of chip design layouts in semiconductor manufacturing and a statistical model creator for creating statistical models based on the known problematic circuit patterns stored in the critical signature databases and a target specification based on deviation between physical measurement and simulation data or design data associated with the known problematic circuit patterns. The system further has a statistical model based predictor for predicting and discovering unknown problematic circuit patterns by applying the statistical models to a large number of candidate circuit patterns generated from a random layout generator, or extracted from the chip design layout based on hot spot sites determined by extended lithographic process check on the chip design layout or inspecting wafers manufactured with the chip design layout with an aggressive sensitivity setting.

摘要翻译： 系统包括用于存储半导体制造中的芯片设计布局的关键签名数据库的关键签名库和用于基于存储在关键签名数据库中的已知有问题的电路图案创建统计模型的统计模型创建者，以及基于物理上的偏差的目标规范 测量和仿真数据或与已知有问题的电路图案相关联的设计数据。 该系统还具有基于统计模型的预测器，用于通过将统计模型应用于从随机布局生成器产生的大量候选电路图案中，或者基于确定的热点位置从芯片设计布局提取来预测和发现未知有问题的电路图案 通过延长光刻工艺检查芯片设计布局或使用激进的灵敏度设置检查使用芯片设计布局制造的晶圆。

公开(公告)号：US09142014B2

公开(公告)日：2015-09-22

申请号：US13906303

申请日：2013-05-30

申请人： DMO Systems Limited

发明人： Jason Zse-Cherng Lin ,  Shauh-Teh Juang

IPC分类号： G06K9/00 ,  G06T7/00

CPC分类号： G06T7/001 ,  G06T2207/10061 ,  G06T2207/20016 ,  G06T2207/30148

摘要： A number of wafers of a same semiconductor device are inspected to generate a plurality of candidate defect lists for identifying systematic defects. Each candidate defect list comprises a plurality of candidate defects obtained from inspecting one of the wafers. Each candidate defect is represented by a plurality of defect attributes including a defect location. The candidate defects in every one or more candidate defect lists are processed as a set by stage one grouping and filtering to generate a stage one defect list for each set. The candidate defects in all the stage one defect lists are then processed together by stage two grouping and filtering to generate a final defect lists for systematic defects. The defect attributes of each defect and a design pattern clip extracted from a design database based on the defect location are used in the hierarchical grouping and filtering.

摘要翻译： 检查相同半导体器件的多个晶片以产生用于识别系统缺陷的多个候选缺陷列表。 每个候选缺陷列表包括从检查晶片之一获得的多个候选缺陷。 每个候选缺陷由包括缺陷位置的多个缺陷属性表示。 每一个或多个候选缺陷列表中的候选缺陷通过一级分组和过滤来处理为一组，以生成每组的一级缺陷列表。 然后通过第二阶段分组和过滤处理所有第一阶段缺陷列表中的候选缺陷，以生成用于系统缺陷的最终缺陷列表。 在分层分组和过滤中使用每个缺陷的缺陷属性和基于缺陷位置从设计数据库提取的设计模式剪辑。

公开(公告)号：US20140355867A1

公开(公告)日：2014-12-04

申请号：US13906303

申请日：2013-05-30

申请人： DMO Systems Limited

发明人： Jason Zse-Cherng Lin ,  Shauh-Teh Juang

IPC分类号： G06T7/00

CPC分类号： G06T7/001 ,  G06T2207/10061 ,  G06T2207/20016 ,  G06T2207/30148

摘要： A number of wafers of a same semiconductor device are inspected to generate a plurality of candidate defect lists for identifying systematic defects. Each candidate defect list comprises a plurality of candidate defects obtained from inspecting one of the wafers. Each candidate defect is represented by a plurality of defect attributes including a defect location. The candidate defects in every one or more candidate defect lists are processed as a set by stage one grouping and filtering to generate a stage one defect list for each set. The candidate defects in all the stage one defect lists are then processed together by stage two grouping and filtering to generate a final defect lists for systematic defects. The defect attributes of each defect and a design pattern clip extracted from a design database based on the defect location are used in the hierarchical grouping and filtering.

摘要翻译： 检查相同半导体器件的多个晶片以产生用于识别系统缺陷的多个候选缺陷列表。 每个候选缺陷列表包括从检查晶片之一获得的多个候选缺陷。 每个候选缺陷由包括缺陷位置的多个缺陷属性表示。 每一个或多个候选缺陷列表中的候选缺陷通过一级分组和过滤来处理为一组，以生成每组的一级缺陷列表。 然后通过第二阶段分组和过滤处理所有第一阶段缺陷列表中的候选缺陷，以生成用于系统缺陷的最终缺陷列表。 在分层分组和过滤中使用每个缺陷的缺陷属性和基于缺陷位置从设计数据库提取的设计模式剪辑。