Invention Application
US20170033161A1 METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF
有权
改善RRAM可靠性的金属线连接，包含该RRAM可靠性的半导体装置及其制造
- Patent Title: METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF
- Patent Title (中): 改善RRAM可靠性的金属线连接，包含该RRAM可靠性的半导体装置及其制造
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Application No.: US15292334Application Date: 2016-10-13
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Publication No.: US20170033161A1Publication Date: 2017-02-02
- Inventor: Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00 ; H01L23/528
Abstract:
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.
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Information query
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