发明申请
US20170033161A1 METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF
有权
改善RRAM可靠性的金属线连接，包含该RRAM可靠性的半导体装置及其制造
- 专利标题： METAL LINE CONNECTION FOR IMPROVED RRAM RELIABILITY, SEMICONDUCTOR ARRANGEMENT COMPRISING THE SAME, AND MANUFACTURE THEREOF
- 专利标题（中）： 改善RRAM可靠性的金属线连接，包含该RRAM可靠性的半导体装置及其制造
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申请号： US15292334申请日： 2016-10-13
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公开(公告)号： US20170033161A1公开(公告)日： 2017-02-02
- 发明人: Chun-Yang Tsai , Yu-Wei Ting , Kuo-Ching Huang
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 主分类号： H01L27/24
- IPC分类号： H01L27/24 ; H01L45/00 ; H01L23/528
摘要：
Some embodiments relate to an integrated circuit device including an array of memory cells disposed over a semiconductor substrate. An array of first metal lines are disposed at a first height over the substrate and are connected to the memory cells of the array. Each of the first metal lines has a first cross-sectional area. An array of second metal lines are disposed at a second height over the substrate and are connected to the memory cells of the array. Each of the second metal lines has a second cross-sectional area which is greater than the first cross-sectional area.
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