Described is an apparatus which comprises: an Intellectual Property (IP) block; control logic operable to send a first command to the IP block to cause the first IP block to enter a first power state from a second power state; and a communicating fabric coupled to the IP block and to the control logic, the communicating fabric to send multiple packets with a first header from the IP block to the control logic after the first command is processed by the IP block, wherein the multiple packets are associated with multiple registers which are identified as registers whose contents are to be saved.