Invention Application
- Patent Title: TRAP LAYER SUBSTRATE STACKING TECHNIQUE TO IMPROVE PERFORMANCE FOR RF DEVICES
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Application No.: US15051197Application Date: 2016-02-23
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Publication No.: US20170110420A1Publication Date: 2017-04-20
- Inventor: Kuo-Yu Cheng , Chih-Ping Chao , Kuan-Chi Tsai , Shih-Shiung Chen , Wei-Kung Tsai
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Main IPC: H01L23/66
- IPC: H01L23/66 ; H01L29/10 ; H01L23/48 ; H01L23/31 ; H01L27/12 ; H01L21/683 ; H01L23/00 ; H01L21/28 ; H01L21/84 ; H01L21/762 ; H01L23/528 ; H01L21/768

Abstract:
Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
Public/Granted literature
- US09761546B2 Trap layer substrate stacking technique to improve performance for RF devices Public/Granted day:2017-09-12
Information query
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