Invention Application
- Patent Title: GENERATION AND APPLICATION OF STRESSMARKS IN A COMPUTER SYSTEM
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Application No.: US15412361Application Date: 2017-01-23
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Publication No.: US20170132006A1Publication Date: 2017-05-11
- Inventor: Ramon Bertran , Pradip Bose , Alper Buyuktosunoglu , Timothy J. Slegel
- Applicant: International Business Machines Corporation
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F11/30 ; G06F11/34 ; G06F15/78

Abstract:
One aspect is a method that includes analyzing, by a processor of an analysis system, an instruction set architecture of a targeted complex-instruction set computer (CISC) processor to generate an instruction set profile for each CISC architectural instruction variant of the instruction set architecture. A combination of instruction sequences for the targeted CISC processor is determined from the instruction set profile that corresponds to a desired stressmark type. The desired stressmark type defines a metric representative of functionality of interest of the targeted CISC processor. Performance of the targeted CISC processor is monitored with respect to the desired stressmark type while executing each of the instruction sequences. The targeted CISC processor is stress tested based on executing at least one of the instruction sequences identified as most closely aligning with the desired stressmark type.
Public/Granted literature
- US10042642B2 Generation and application of stressmarks in a computer system Public/Granted day:2018-08-07
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