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公开(公告)号：US20240314151A1
公开(公告)日：2024-09-19
申请号：US18185318
申请日：2023-03-16
IPC分类号： H04L9/40
CPC分类号： H04L63/1425 , H04L63/1441
摘要： Provided are a computer program product, system, and method for detecting anomalous activity in a system-on-chip. Counter values are determined from counters for processing elements in the system-on-chip during a test workload. A counter for one of the processing elements indicates an amount of activity at a processing element during a measurement period. An anomaly detector is trained to classify the determined counter values during measurement periods occurring during the test workload as non-anomalous activity. The trained anomaly detector is deployed within the system-on-chip to process counter values in the counters for the processing elements on the system-on-chip to classify the counter values as anomalous or non-anomalous. A mitigation action is performed in response to the deployed trained anomaly detector detecting the anomalous activity within the system-on-chip.
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公开(公告)号：US20230281518A1
公开(公告)日：2023-09-07
申请号：US17687074
申请日：2022-03-04
发明人： Dinesh C. Verma , Supriyo Chakraborty , Shiqiang Wang , Augusto Vega , Hazar Yueksel , Ashish Verma , Pradip Bose , Jayaram Kallapalayam Radhakrishnan
IPC分类号： G06N20/20
CPC分类号： G06N20/20
摘要： Second machine learning models trained using respective second data sets can be received. The second machine learning models can be run using a first data set used in training a first machine learning model, where the second machine learning models produce respective outputs. Scores associated with the second machine learning models can be determined by comparing the respective outputs with ground truth associated with the first data set. Based on the scores associated with the second machine learning models, whether the first data set is to be discarded or kept can be determined for training the first machine learning model.
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公开(公告)号：US11720469B1
公开(公告)日：2023-08-08
申请号：US18054603
申请日：2022-11-11
CPC分类号： G06F11/3414 , G06F11/3075 , G06F11/3466
摘要： A computer-implemented method, a computer system and a computer program product customize generation and application of stress test conditions in a processor core. The method includes receiving a workload at the processor core, where the workload includes a plurality of instructions and the processor core comprises a plurality of macros. The method also includes obtaining macro performance data for each macro in the plurality of macros from the processor core. The method further includes determining a switching activity level for each macro in the plurality of macros when each instruction in the plurality of instructions is run based on the macro performance data. Lastly, the method includes generating a stressmark comprising the plurality of instructions in the workload, where the stressmark is associated with a macro in the plurality of macros when the switching activity level for the macro is above a minimum threshold.
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公开(公告)号：US11693728B2
公开(公告)日：2023-07-04
申请号：US17650727
申请日：2022-02-11
发明人： Giora Biran , Pradip Bose , Alper Buyuktosunoglu , Pierce I-Jen Chuang , Preetham M. Lobo , Ramon Bertran Monfort , Phillip John Restle , Christos Vezyrtzis , Tobias Webel
CPC分类号： G06F11/0793 , G06F1/28 , G06F1/305 , G06F1/324 , G06F9/3836 , G06F11/0721
摘要： Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
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公开(公告)号：US20230161639A1
公开(公告)日：2023-05-25
申请号：US18150894
申请日：2023-01-06
发明人： Augusto Vega , Alper Buyuktosunoglu , Pradip Bose , Vaidyanathan Srinivasan , Ranjal Gautham Shenoy
CPC分类号： G06F9/5083 , G06N20/00 , G06F9/5044 , G06F9/5061 , G06N5/043
摘要： Systems, computer-implemented methods and/or computer program products that facilitate management of resources are provided. In one embodiment, a computer-implemented method comprises: employing, by a system operatively coupled to a processor, at least one model to predict respective token needs by a set of processing elements during execution of a workload; and exchanging, by the system, one or more tokens between a subset of the processing elements as a function of the predicted token needs.
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公开(公告)号：US11360772B2
公开(公告)日：2022-06-14
申请号：US16836794
申请日：2020-03-31
摘要： Embodiments for implementing optimized accelerators in a computing environment are provided. Selected instruction sequence code blocks derived from one or more application workloads may be consolidated together to activate one or more accelerators subject to one or more constraints and projections.
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公开(公告)号：US20220164250A1
公开(公告)日：2022-05-26
申请号：US17650727
申请日：2022-02-11
发明人： Giora Biran , Pradip Bose , Alper Buyuktosunoglu , Pierce I-Jen Chuang , Preetham M. Lobo , Ramon Bertran Monfort , Phillip John Restle , Christos Vezyrtzis , Tobias Webel
摘要： Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
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公开(公告)号：US11275644B2
公开(公告)日：2022-03-15
申请号：US16706195
申请日：2019-12-06
发明人： Giora Biran , Pradip Bose , Alper Buyuktosunoglu , Pierce I-Jen Chuang , Preetham M. Lobo , Ramon Bertran Monfort , Phillip John Restle , Christos Vezyrtzis , Tobias Webel
摘要： Techniques facilitating voltage droop reduction and/or mitigation in a processor core are provided. In one example, a system can comprise a memory that stores, and a processor that executes, computer executable components. The computer executable components can comprise an observation component that detects one or more events at a first stage of a processor pipeline. An event of the one or more events can be a defined event determined to increase a level of power consumed during a second stage of the processor pipeline. The computer executable components can also comprise an instruction component that applies a voltage droop mitigation countermeasure prior to the increase of the level of power consumed during the second stage of the processor pipeline and a feedback component that provides a notification to the instruction component that indicates a success or a failure of a result of the voltage droop mitigation countermeasure.
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公开(公告)号：US11151002B2
公开(公告)日：2021-10-19
申请号：US16377131
申请日：2019-04-05
摘要： A computer system that has two or more processing engines (PE), each capable of performing one or more operations on one or more operands but one or more of the PEs performs the operations unreliably. Initial results of each operation are debiased to create a debiased result used by the system instead of the initial result. The debiased result has an expected value equal to a correct output where the correct output is the initial result the respective operation would have produced if the respective operation performed was reliable.
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公开(公告)号：US11037650B2
公开(公告)日：2021-06-15
申请号：US16774505
申请日：2020-01-28
发明人： Alper Buyuktosunoglu , Swagath Venkataramani , Rajiv Joshi , Karthik V. Swaminathan , Schuyler Eldridge , Pradip Bose
摘要： A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
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