Invention Application
- Patent Title: PATTERN PLACEMENT ERROR COMPENSATION LAYER IN VIA OPENING
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Application No.: US14939319Application Date: 2015-11-12
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Publication No.: US20170141036A1Publication Date: 2017-05-18
- Inventor: Deniz E. Civay , Erik R. Hosler
- Applicant: GLOBALFOUNDRIES Inc.
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L23/532 ; H01L21/768

Abstract:
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
Public/Granted literature
- US09748176B2 Pattern placement error compensation layer in via opening Public/Granted day:2017-08-29
Information query
IPC分类: