A latency time of memory access is suppressed.A memory controller includes memory control units and a connection switching unit. The memory control units each independently generate a request to a memory on the basis of a command from a computer. Any one of the memory control units and the memory are connected in response to a connection request from each of the memory control units, and the request is output to the memory. A memory system is constituted of the memory and the memory controller. An information processing system is constituted of the memory system and the computer.