公开(公告)号：US20170160952A1

公开(公告)日：2017-06-08

申请号：US15323810

申请日：2015-06-09

Applicant: SONY CORPORATION

Inventor： KENICHI NAKANISHI ,  HIROYUKI IWAKI ,  KEN ISHII ,  RYOJI IKEGAYA ,  KENTAROU MORI

IPC: G06F3/06 ,  G06F12/14 ,  G06F11/10 ,  G06F13/40

CPC classification number: G06F3/0611 ,  G06F3/0614 ,  G06F3/0623 ,  G06F3/0647 ,  G06F3/0679 ,  G06F11/1044 ,  G06F12/1408 ,  G06F12/16 ,  G06F13/4022 ,  G06F2212/1052 ,  G06F2212/402

Abstract: A latency time of memory access is suppressed.A memory controller includes memory control units and a connection switching unit. The memory control units each independently generate a request to a memory on the basis of a command from a computer. Any one of the memory control units and the memory are connected in response to a connection request from each of the memory control units, and the request is output to the memory. A memory system is constituted of the memory and the memory controller. An information processing system is constituted of the memory system and the computer.