A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a row decoder circuit connected to the memory cell array through a plurality of word lines; and a page buffer circuit connected to the memory cell array through bit lines. The row decoder circuit applies read voltages to a selected word line during a read operation.During a read operation performed with respect to each of N logical pages (N being a positive integer) of memory cells connected to the selected word line, the row decoder circuit applies a read voltage from among adjacent N read voltages to the selected word line without applying read voltages other than the adjacent N read voltages to the selected word line. The adjacent N read voltages include a second highest read voltage among the read voltages.