- 专利标题: Method of Semiconductor Integrated Circuit Fabrication
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申请号: US15430852申请日: 2017-02-13
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公开(公告)号: US20170170066A1公开(公告)日: 2017-06-15
- 发明人: Ching-Fu Yeh , Chao-Hsien Peng , Hsien-Chang Wu , Hsiang-Huan Lee
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 主分类号: H01L21/768
- IPC分类号: H01L21/768 ; H01L21/027 ; H01L21/02 ; H01L21/3213
摘要:
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.
公开/授权文献
- US09947583B2 Method of semiconductor integrated circuit fabrication 公开/授权日:2018-04-17
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