公开(公告)号：US09947583B2

公开(公告)日：2018-04-17

申请号：US15430852

申请日：2017-02-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/027 ,  H01L21/02

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US20170170066A1

公开(公告)日：2017-06-15

申请号：US15430852

申请日：2017-02-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3213

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US09570347B2

公开(公告)日：2017-02-14

申请号：US14733487

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/027 ,  H01L21/3213 ,  B82Y40/00

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供衬底并在衬底上沉积导电层。 在导电层上形成图案化的硬掩模和催化剂层。 该方法还包括从催化剂层生长多个碳纳米管（CNT）并通过使用CNT和图案化的硬掩模作为蚀刻掩模来蚀刻导电层以形成金属特征。

公开(公告)号：US09054161B2

公开(公告)日：2015-06-09

申请号：US14266069

申请日：2014-04-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Hsiang-Huan Lee ,  Chao-Hsien Peng ,  Hsien-Chang Wu

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  B82Y40/00

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供衬底并在衬底上沉积导电层。 在导电层上形成图案化的硬掩模和催化剂层。 该方法还包括从催化剂层生长多个碳纳米管（CNT）并通过使用CNT和图案化的硬掩模作为蚀刻掩模来蚀刻导电层以形成金属特征。

公开(公告)号：US10930552B2

公开(公告)日：2021-02-23

申请号：US16658862

申请日：2019-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L21/027 ,  H01L21/3213 ,  B82Y40/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US09935006B2

公开(公告)日：2018-04-03

申请号：US15447251

申请日：2017-03-02

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsien-Chang Wu ,  Li-Lin Su

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76882 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295

摘要： The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.

公开(公告)号：US09589897B1

公开(公告)日：2017-03-07

申请号：US14828585

申请日：2015-08-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hsien-Chang Wu ,  Li-Lin Su

IPC分类号： H01L21/48 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76882 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295

摘要： The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is formed that extends through a plurality of layers over a substrate. A barrier layer is formed on surfaces of the opening. A liner layer is formed over the barrier layer in the opening. The barrier layer and the liner layer have different material compositions. The opening is filled with a non-copper metal material. The non-copper material is formed over the liner layer. In some embodiments, the non-copper metal material includes cobalt.

摘要翻译： 本公开涉及在半导体技术节点中制造半导体器件的方法，其半导体技术节点为5纳米或更小。 形成了在衬底上延伸穿过多个层的开口。 在开口的表面上形成阻挡层。 在开口中的阻挡层的上方形成衬垫层。 阻挡层和衬层具有不同的材料组成。 开口填充有非铜金属材料。 非铜材料形成在衬层上。 在一些实施例中，非铜金属材料包括钴。

公开(公告)号：US20200051857A1

公开(公告)日：2020-02-13

申请号：US16658862

申请日：2019-10-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/532

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US10453746B2

公开(公告)日：2019-10-22

申请号：US15953708

申请日：2018-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L21/027 ,  H01L21/3213 ,  B82Y40/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

公开(公告)号：US20150270170A1

公开(公告)日：2015-09-24

申请号：US14733487

申请日：2015-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ching-Fu Yeh ,  Chao-Hsien Peng ,  Hsien-Chang Wu ,  Hsiang-Huan Lee

IPC分类号： H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3213

CPC分类号： H01L21/76892 ,  B82Y40/00 ,  H01L21/02115 ,  H01L21/02697 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/76838 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

摘要： A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

摘要翻译： 公开了制造半导体集成电路（IC）的方法。 该方法包括提供衬底并在衬底上沉积导电层。 在导电层上形成图案化的硬掩模和催化剂层。 该方法还包括从催化剂层生长多个碳纳米管（CNT）并通过使用CNT和图案化的硬掩模作为蚀刻掩模来蚀刻导电层以形成金属特征。