Invention Application
- Patent Title: SEMICONDUCTORS, PACKAGES, WAFER LEVEL PACKAGES, AND METHODS OF MANUFACTURING THE SAME
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Application No.: US15243296Application Date: 2016-08-22
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Publication No.: US20170170127A1Publication Date: 2017-06-15
- Inventor: Hyeong Seok CHOI , Ki Jun SUNG , Jong Hoon KIM , Young Geun YOO , Pil Soon BAE
- Applicant: SK hynix Inc.
- Priority: KR10-2015-0177492 20151211; KR10-2016-0034059 20160322
- Main IPC: H01L23/544
- IPC: H01L23/544 ; H01L23/00 ; H01L23/31 ; H01L23/498

Abstract:
According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.
Public/Granted literature
- US09837360B2 Wafer level packages and electronics system including the same Public/Granted day:2017-12-05
Information query
IPC分类: