公开(公告)号：US20150064843A1

公开(公告)日：2015-03-05

申请号：US14536002

申请日：2014-11-07

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI

IPC: H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/80001 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1011 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/4801 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.

Abstract translation: 堆叠半导体封装包括具有第一表面和第二表面的第一半导体芯片，第一表面和第二表面背离第一表面，并且包括形成在第一表面上的第一焊盘和穿过第一表面的第一贯穿电极， ; 第二半导体芯片，堆叠在第一半导体芯片的第二表面上，并且包括形成在面向第一半导体芯片的第三表面上的第二焊盘和穿过第三表面的第二贯通电极以及背离第一半导体芯片的第四表面 第三表面并与第一贯通电极电连接; 以及模制部件，其形成为基本上覆盖所述堆叠的第一和第二半导体芯片，并且具有露出设置在所述第一半导体芯片的第一表面上的所述第一贯穿电极的一端的开口。

公开(公告)号：US20230386977A1

公开(公告)日：2023-11-30

申请号：US18450216

申请日：2023-08-15

Applicant: SK hynix Inc.

Inventor： Seung Hwan KIM ,  Hyun Chul SEO ,  Hyeong Seok CHOI ,  Moon Un HYUN

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5386 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/73 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/14335 ,  H01L2224/08146 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/16148

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

公开(公告)号：US20160099229A1

公开(公告)日：2016-04-07

申请号：US14621156

申请日：2015-02-12

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/06181 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/17505 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/381 ,  H01L2924/00014

Abstract: A semiconductor device includes a substrate having a first surface and a second surface that are opposite to each other, a plurality of through electrodes penetrating the substrate and extending from the first surface to the second surface, front-side bumps disposed on the first surface and connected to odd-numbered through electrodes among the plurality of through electrodes, and backside bumps disposed on the second surface and connected to even-numbered through electrodes among the plurality of through electrodes. Related semiconductor packages, fabrication methods, electronic systems and memory cards are also provided.

Abstract translation: 半导体器件包括具有彼此相对的第一表面和第二表面的基板，穿过基板并从第一表面延伸到第二表面的多个贯穿电极，设置在第一表面上的前侧凸块和 连接到多个贯通电极中的奇数通电极，以及设置在第二表面上并与多个贯通电极中的偶数通电极连接的背面凸块。 还提供了相关的半导体封装，制造方法，电子系统和存储卡。

公开(公告)号：US20150243619A1

公开(公告)日：2015-08-27

申请号：US14707910

申请日：2015-05-08

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3128 ,  H01L23/482 ,  H01L24/17 ,  H01L25/03 ,  H01L25/04 ,  H01L25/0657 ,  H01L2224/13017 ,  H01L2224/16145 ,  H01L2224/1705 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12042 ,  H01L2924/1434 ,  H01L2924/182 ,  H01L2924/00

Abstract: A conductive bump includes a step member formed to form a step on a portion of a connection pad; and a conductive member formed on the connection pad and the step member and having an inclined surface which is inclined with respect to the connection pad.

Abstract translation: 导电凸块包括形成为在连接焊盘的一部分上形成台阶的台阶部件; 以及形成在连接焊盘和台阶部件上并具有相对于连接焊盘倾斜的倾斜表面的导电部件。

公开(公告)号：US20130292845A1

公开(公告)日：2013-11-07

申请号：US13693678

申请日：2012-12-04

Applicant: SK HYNIX INC.

Inventor： Hyeong Seok CHOI

IPC: H01L23/498 ,  H01L21/78

CPC classification number: H01L25/50 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/83 ,  H01L24/89 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/80001 ,  H01L2224/83851 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/1011 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/4801 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor chip having a first surface and a second surface which faces away from the first surface and including first bonding pads which are formed on the first surface and first through electrodes which pass through the first surface and the second surface; a second semiconductor chip stacked over the second surface of the first semiconductor chip, and including second bonding pads which are formed on a third surface facing the first semiconductor chip and second through electrodes which pass through the third surface and a fourth surface facing away from the third surface and are electrically connected with the first through electrodes; and a molding part formed to substantially cover the stacked first and second semiconductor chips and having openings which expose one end of the first through electrodes disposed on the first surface of the first semiconductor chip.

公开(公告)号：US20130078807A1

公开(公告)日：2013-03-28

申请号：US13680668

申请日：2012-11-19

Applicant: SK HYNIX INC.

Inventor： Chang Jun PARK ,  Kwon Whan HAN ,  Seong Cheol KIM ,  Sung Min KIM ,  Hyeong Seok CHOI ,  Ha Na LEE ,  Tac Keun OH ,  Sang Joon LIM

IPC: H01L21/48

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/367 ,  H01L23/552 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/94 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01059 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/3025 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A wafer level chip scale package having an enhanced heat exchange efficiency with an EMF shield is presented. The wafer level chip scale package includes a semiconductor chip, an insulation layer, and a metal plate. The semiconductor chip has a plurality of bonding pads on an upper face thereof. The insulation layer is disposed over the upper face of the semiconductor chip and has openings that expose some portions of the bonding pads. The metal plate covers an upper face of the insulation layer and side faces of the semiconductor chip in which the metal plate is electrically insulated from the bonding pads.

公开(公告)号：US20220208648A1

公开(公告)日：2022-06-30

申请号：US17322557

申请日：2021-05-17

Applicant: SK hynix Inc.

Inventor： Seung Hwan KIM ,  Hyun Chul SEO ,  Hyeong Seok CHOI ,  Moon Un HYUN

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

公开(公告)号：US20170373041A1

公开(公告)日：2017-12-28

申请号：US15405619

申请日：2017-01-13

Applicant: SK hynix Inc.

Inventor： Tae Hoon KIM ,  Jong Hoon KIM ,  Dae Won KIM ,  Hyeong Seok CHOI

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/295 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/01029 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443

Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.

公开(公告)号：US20170170127A1

公开(公告)日：2017-06-15

申请号：US15243296

申请日：2016-08-22

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI ,  Ki Jun SUNG ,  Jong Hoon KIM ,  Young Geun YOO ,  Pil Soon BAE

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/544 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/498 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/552 ,  H01L23/562 ,  H01L24/14 ,  H01L24/19 ,  H01L24/97 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83132 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83

Abstract: According to various embodiments, there may be provided packages, semiconductors, and wafer level packages, and there may be provided methods of manufacturing packages, semiconductors, and wafer level packages. A method of manufacturing a wafer level package may include forming alignment marks at a surface of a protection wafer, mounting semiconductor dice on the protection wafer using the alignment marks, forming a first dielectric layer covering the semiconductor dice, planarizing a top surface of the first photosensitive layer, exposuring and developing portions of the planarized first dielectric layer to form opening portions exposing portions of the semiconductor dice, and forming redistribution lines on the first photosensitive dielectric layer. A second dielectric layer may be formed to cover the redistribution lines. Related wafer level packages may also be provided.

公开(公告)号：US20160293565A1

公开(公告)日：2016-10-06

申请号：US14831463

申请日：2015-08-20

Applicant: SK hynix Inc.

Inventor： Hyeong Seok CHOI

IPC: H01L23/00

CPC classification number: H01L24/72 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/90 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/0756 ,  H01L25/117 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05647 ,  H01L2224/13012 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13078 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13191 ,  H01L2224/13193 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2224/90

Abstract: A semiconductor package may include a first substrate and a second substrate. Socket bumps may be disposed on the first substrate to provide insertion grooves within the socket bumps. Plug bumps may be disposed on the second substrate. The plug bumps may be configured for insertion into the insertion grooves of the socket bumps and may electrically connect to the socket bumps. Related memory cards and electronic systems may also be provided.

Abstract translation: 半导体封装可以包括第一衬底和第二衬底。 插座凸块可以设置在第一基板上，以在插座凸块内提供插入槽。 插头凸块可以设置在第二基板上。 插头凸块可以被配置为插入到插座凸块的插入槽中，并且可以电连接到插座凸块。 还可以提供相关的存储卡和电子系统。